Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12385975 | Integrated circuits including error protection of fields in transferred information and field-based error signals and related methods | Farzane Zokaee, Richard James Shannon, Jared Eric Bendt | 2025-08-12 |
| 12182417 | Address-range memory mirroring in a computer system, and related methods | Nagi Aboulenein, Matthew Robert Erler, Shivnandan Kaushik, Donald Scott Phillips | 2024-12-31 |
| 11966750 | System-on-chip management controller | Shivnandan Kaushik, Harb Abdulhamid, Vanshidhar Konda, Yogesh Bansal, Sachhidh Kannan | 2024-04-23 |
| 11847012 | Method and apparatus to provide an improved fail-safe system for critical and non-critical workloads of a computer-assisted or autonomous driving vehicle | Christopher J. Cormack, Matthew Curfman | 2023-12-19 |
| 9594648 | Controlling non-redundant execution in a redundant multithreading (RMT) processor | Glenn J. Hinton, Steven Raasch, John G. Holm, Ronak Singhal, Avinash Sodani +1 more | 2017-03-14 |
| 9405545 | Method and apparatus for cutting senior store latency using store prefetching | Stanislav Shwartsman, Melih Ozgul, Shlomo Raikin, Raanan Sade, Ron Shalev | 2016-08-02 |
| 9081688 | Obtaining data for redundant multithreading (RMT) execution | Glenn J. Hinton, Steven Raasch, John G. Holm, Ronak Singhal, Avinash Sodani +4 more | 2015-07-14 |
| 8793689 | Redundant multithreading processor | Glenn J. Hinton, Steven Raasch, Avinash Sodani, John G. Holm, Ronak Singhal +1 more | 2014-07-29 |
| 7752423 | Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor | Haitham Akkary | 2010-07-06 |
| 7640419 | Method for and a trailing store buffer for use in memory renaming | Per Hammarlund | 2009-12-29 |
| 7603527 | Resolving false dependencies of speculative load instructions | Zhongying Zhang, Per Hammarlund | 2009-10-13 |
| 7590784 | Detecting and resolving locks in a memory unit | Prakash Math, Matthew C. Merten, Beeman C. Strong, Morris Marden, David William Burns | 2009-09-15 |
| 7516313 | Predicting contention in a processor | Bratin Saha, Matthew C. Merten, David A. Koufaty, Per Hammarlund | 2009-04-07 |
| 7475225 | Method and apparatus for microarchitecture partitioning of execution clusters | Stephan Jourdan, Avinash Sodani, Alexandre J. Farcy, Per Hammarlund, Mark Charles Davis | 2009-01-06 |
| 7457932 | Load mechanism | Per Hammarlund, Stephan Jourdan, Michael A. Fetterman, Glenn J. Hinton, Ronak Singhal | 2008-11-25 |
| 7418552 | Memory disambiguation for large instruction windows | Haitham Akkary | 2008-08-26 |
| 7174428 | Method and system for transforming memory location references in instructions | Per Hammarlund, Avinash Sodani | 2007-02-06 |
| 7130965 | Apparatus and method for store address for store address prefetch and line locking | Per Hammarlund, Stephan Jourdan, Aravindh Baktha, Hermann W. Gartler | 2006-10-31 |
| 6591342 | Memory disambiguation for large instruction windows | Haitham Akkary | 2003-07-08 |