Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399780 | Firmware first handling of a machine check event | Sarathy Jayakumar, Eswar Konduru | 2025-08-26 |
| 12360847 | Adaptive internal error scrubbing and error handling | Kuljit S. Bains, Kjersten E. Criss, Rajat Agarwal, Omar Avelar Suarez, Subhankar Panda +3 more | 2025-07-15 |
| 12235720 | Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS) | Rajat Agarwal, Hsing-Min Chen, Wei-Pin Chen, Wei Wu, Jing Ling +7 more | 2025-02-25 |
| 12189468 | Cloud scale server reliability management | Theodros Yigzaw, Subhankar Panda, Hugo Enrique Gonzalez Chavero, Satyaprakash Nanda, Omar Avelar Suarez +1 more | 2025-01-07 |
| 12044730 | Device, system, and method to concurrently store multiple PMON counts in a single register | Gaurav Porwal, Subhankar Panda, Theodros Yigzaw | 2024-07-23 |
| 11687391 | Serializing machine check exceptions for predictive failure analysis | Gaurav Porwal, Subhankar Panda | 2023-06-27 |
| 11307996 | Hardware unit for reverse translation in a processor | Sarathy Jayakumar, Ashok Raj, Wei-Pin Chen, Theodros Yigzaw | 2022-04-19 |
| 11163623 | Serializing machine check exceptions for predictive failure analysis | Gaurav Porwal, Subhankar Panda | 2021-11-02 |
| 10824496 | Apparatus and method for vectored machine check bank reporting | Subhankar Panda, Gaurav Porwal | 2020-11-03 |
| 10671465 | Serializing machine check exceptions for predictive failure analysis | Gaurav Porwal, Subhankar Panda | 2020-06-02 |
| 10474596 | Providing dedicated resources for a system management mode of a processor | Sarathy Jayakumar, Ashok Raj, Narayan Ranganathan, Mohan J. Kumar, Sergiu D. Ghetie | 2019-11-12 |
| 9772844 | Common architectural state presentation for processor having processing cores of different types | Bret L. Toll, Jason W. Brandt | 2017-09-26 |
| 9594648 | Controlling non-redundant execution in a redundant multithreading (RMT) processor | Glenn J. Hinton, Steven Raasch, Sebastien Hily, Ronak Singhal, Avinash Sodani +1 more | 2017-03-14 |
| 9367325 | Common architecture state presentation for processor having processing cores of different types | Bret L. Toll, Jason W. Brandt | 2016-06-14 |
| 9141454 | Signaling software recoverable errors | Ashok Raj, Gilbert Neiger, Rajesh M. Sankaran, Mohan J. Kumar | 2015-09-22 |
| 9081688 | Obtaining data for redundant multithreading (RMT) execution | Glenn J. Hinton, Steven Raasch, Sebastien Hily, Ronak Singhal, Avinash Sodani +4 more | 2015-07-14 |
| 8793689 | Redundant multithreading processor | Glenn J. Hinton, Steven Raasch, Avinash Sodani, Sebastien Hily, Ronak Singhal +1 more | 2014-07-29 |
| 8122230 | Using a processor identification instruction to provide multi-level processor topology information | Leena K. Puthiyedath, James B. Crossland, Martin G. Dixon, Raicsh Parthasarathy | 2012-02-21 |
| 8095932 | Providing quality of service via thread priority in a hyper-threaded microprocessor | Matthew C. Merten, Santhosh Srinath, Morris Marden, Glenn J. Hinton | 2012-01-10 |