AF

Alexandre J. Farcy

IN Intel: 30 patents #1,238 of 30,777Top 5%
Overall (All Time): #122,742 of 4,157,543Top 3%
30
Patents All Time

Issued Patents All Time

Showing 25 most recent of 30 patents

Patent #TitleCo-InventorsDate
11900108 Rotate instructions that complete execution either without writing or reading flags Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2024-02-13
11106461 Rotate instructions that complete execution either without writing or reading flags Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2021-08-31
10649774 Multiplication instruction for which execution completes without writing a carry flag Vinodh Gopal, James D. Guilford, Wajdi K. Feghali, Erdinc Ozturk, Gilbert M. Wolrich +5 more 2020-05-12
10409612 Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy +4 more 2019-09-10
10409611 Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy +4 more 2019-09-10
9990201 Multiplication instruction for which execution completes without writing a carry flag Vinodh Gopal, James D. Guilford, Wajdi K. Feghali, Erdine Ozturk, Gilbert M. Wolrich +5 more 2018-06-05
9940131 Rotate instructions that complete execution either without writing or reading flags Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2018-04-10
9940130 Rotate instructions that complete execution either without writing or reading flags Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2018-04-10
9916160 Rotate instructions that complete execution either without writing or reading flags Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2018-03-13
9524191 Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements Morris Marden, Matthew C. Merten, Avinash Sodani, James Hadley, Ilhyun Kim 2016-12-20
9354875 Enhanced loop streaming detector to drive logic optimization Matthew C. Merten, Justin M. Deinlein, Yury N. Ilin, Tong Li, Srikanth Srinivasan 2016-05-31
9348591 Multi-level tracking of in-use state of cache lines Ilhyun Kim, Chen Koren, Robert L. Hinton, Choon Wei Khor, Lihu Rappoport 2016-05-24
9280492 System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registers Paul Caprioli 2016-03-08
9164762 Rotate instructions that complete execution without reading carry flag Vinodh Gopal, James D. Gulilford, Gilbert M. Wolrich, Waidi K. Feghali, Erdinc Ozturk +5 more 2015-10-20
9158696 Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses Ilhyun Kim, Choon Wei Khor, Robert L. Hinton 2015-10-13
8825989 Technique to perform three-source operations Avinash Sodani, Stephan Jourdan, Per Hammarlund 2014-09-02
8738893 Add instructions to add three source operands Vindoh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2014-05-27
8589663 Technique to perform three-source operations Avinash Sodani, Stephan Jourdan, Per Hammarlund 2013-11-19
8549264 Add instructions to add three source operands Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2013-10-01
8521993 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Morris Marden, Matthew C. Merten, Avinash Sodani, James Hadley, Ilhyun Kim 2013-08-27
8504807 Rotate instructions that complete execution without reading carry flag Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk +5 more 2013-08-06
8504804 Managing multiple threads in a single pipeline Matthew C. Merten, Avinash Sodani, James Hadley, Iredamola Olopade 2013-08-06
8438369 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Morris Marden, Matthew C. Merten, Avinash Sodani, James Hadley, Ilhyun Kim 2013-05-07
8402253 Managing multiple threads in a single pipeline Matthew C. Merten, Avinash Sodani, James Hadley, Iredamola Olopade 2013-03-19
8291196 Forward-pass dead instruction identification and removal at run-time Stephan Jourdan, Matthew C. Merten 2012-10-16