Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9348591 | Multi-level tracking of in-use state of cache lines | Ilhyun Kim, Chen Koren, Alexandre J. Farcy, Robert L. Hinton, Lihu Rappoport | 2016-05-24 |
| 9158696 | Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses | Ilhyun Kim, Alexandre J. Farcy, Robert L. Hinton | 2015-10-13 |