Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11620243 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2023-04-04 |
| 10884959 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2021-01-05 |
| 10409763 | Apparatus and method for efficiently implementing a processor pipeline | Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Polychronis Xekalakis +7 more | 2019-09-10 |
| 10089239 | Memory system architecture | Shinye Shiu, Chih-Chung Chang, Vyacheslav V. Malyugin, Santhosh Rao | 2018-10-02 |
| 9477628 | Collective communications apparatus and method for parallel systems | David Keppel, Dong Hyuk Woo, Joshua B. Fryman | 2016-10-25 |
| 9459871 | System of improved loop detection and execution | Masha Lipshits, Lihu Rappaport, Shantanu Gupta, Franck Sala, Naveen Kumar | 2016-10-04 |
| 9459949 | Methods and apparatus to provide failure detection | Joshua B. Fryman | 2016-10-04 |
| 9195465 | Cache coherency and processor consistency | Varun K. Mohandru, Fernando Latorre, Li-Gao Zei, Rami May, Lutz Naethke | 2015-11-24 |
| 8904028 | Scalable cluster router | Gianluca Iannaccone, Sylvia Ratnasamy, Maziar H. Manesh, Katerina Argyraki, Byung-Gon Chun +4 more | 2014-12-02 |
| 8832505 | Methods and apparatus to provide failure detection | Joshua B. Fryman | 2014-09-09 |
| 7680990 | Superword memory-access instructions for data processor | Donald Soltis, Dale Morris, Dean Mulla, Achmed R. Zahir, Amy O'Donnell | 2010-03-16 |
| 7143270 | System and method for adding an instruction to an instruction set architecture | Kevin Rudd, Dale Morris, James M. Hull | 2006-11-28 |