Issued Patents All Time
Showing 25 most recent of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020027 | Convolutional neural network on programmable two dimensional image processor | Ofer Shacham, David Patterson, William R. Mark, Daniel Frederic Finchelstein, Jason Redgrave | 2024-06-25 |
| 11706010 | Methods and apparatus for providing redundant networking capabilities for teleoperations | Zhan Xiong Chin, Young Jean (Albert) Han | 2023-07-18 |
| 11620243 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2023-04-04 |
| 11544060 | Two dimensional masked shift instruction | — | 2023-01-03 |
| 11481884 | Image quality enhancement for autonomous vehicle remote operations | Yichao (Roger) Shen, Alexandr Bakhturin, Chenjie Luo, Ian Zhou, Hubert Hua Kian Teo +1 more | 2022-10-25 |
| 11321802 | Large lookup tables for an image processor | Dustin Michael DeWeese | 2022-05-03 |
| 11250537 | Configurable and programmable image processor unit | Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more | 2022-02-15 |
| 11196953 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave, Ofer Shacham | 2021-12-07 |
| 11190718 | Line buffer unit for image processor | Neeti Desai, Qiuling Zhu, Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein | 2021-11-30 |
| 11182138 | Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure | — | 2021-11-23 |
| 11153464 | Two dimensional shift array for image processor | Ofer Shacham, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2021-10-19 |
| 11140293 | Sheet generator for image processor | Jason Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein | 2021-10-05 |
| 11138013 | Energy efficient processor core architecture for image processor | Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2021-10-05 |
| 11030005 | Configuration of application software on multi-core image processor | Hyunchul Park | 2021-06-08 |
| 10996988 | Program code transformations to improve image processor runtime efficiency | Hyunchul Park | 2021-05-04 |
| 10915773 | Statistics operations on two dimensional image processor | Edward Chang, Daniel Frederic Finchelstein, Szepo Robert Hung, Ofer Shacham | 2021-02-09 |
| 10915319 | Two dimensional masked shift instruction | — | 2021-02-09 |
| 10884959 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2021-01-05 |
| 10872393 | Image processor with high throughput internal communication protocol | Jason Redgrave, Qiuling Zhu, Ji Kim, Artem Vasilyev, Ofer Shacham | 2020-12-22 |
| 10853908 | Image processor complex transfer functions | — | 2020-12-01 |
| 10789505 | Convolutional neural network on programmable two dimensional image processor | Ofer Shacham, David Patterson, William R. Mark, Daniel Frederic Finchelstein, Jason Redgrave | 2020-09-29 |
| 10789202 | Image processor with configurable number of active cores and supporting internal network | Jason Redgrave, Ji Kim, Ofer Shacham | 2020-09-29 |
| 10791284 | Virtual linebuffers for image signal processors | Qiuling Zhu, Ofer Shacham, Jason Redgrave, Daniel Frederic Finchelstein | 2020-09-29 |
| 10754654 | Energy efficient processor core architecture for image processor | Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2020-08-25 |
| 10733956 | Macro I/O unit for image processor | Neeti Desai, Dilan Manatunga, Jason Redgrave, William R. Mark | 2020-08-04 |