Issued Patents All Time
Showing 25 most recent of 193 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12259575 | Clock signal distribution using photonic fabric | Philip Winterbottom, Martinus Bos | 2025-03-25 |
| 12229865 | Graphics processor with non-blocking concurrent architecture | Luke T. Peterson, James Alexander McCombe, Steven J. Clohset | 2025-02-18 |
| 12217328 | Multistage collector for outputs in multiprocessor systems | James Alexander McCombe, Steven J. Clohset, Luke T. Peterson | 2025-02-04 |
| 12020027 | Convolutional neural network on programmable two dimensional image processor | Ofer Shacham, David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein | 2024-06-25 |
| 11880925 | Atomic memory update unit and methods | Steven J. Clohset, Luke T. Peterson | 2024-01-23 |
| 11830102 | Synchronized data chaining using on-chip cache | Benjamin K. Dodge, Xiaoyu Ma | 2023-11-28 |
| 11699210 | Multistage collector for outputs in multiprocessor systems | James Alexander McCombe, Steven J. Clohset, Luke T. Peterson | 2023-07-11 |
| 11625885 | Graphics processor with non-blocking concurrent architecture | Luke T. Peterson, James Alexander McCombe, Steven J. Clohset | 2023-04-11 |
| 11620243 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2023-04-04 |
| 11443402 | Synchronized data chaining using on-chip cache | Benjamin K. Dodge, Xiaoyu Ma | 2022-09-13 |
| 11257271 | Atomic memory update unit and methods | Steven J. Clohset, Luke T. Peterson | 2022-02-22 |
| 11250537 | Configurable and programmable image processor unit | Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more | 2022-02-15 |
| 11227362 | Multistage collector for outputs in multiprocessor systems | James Alexander McCombe, Steven J. Clohset, Luke T. Peterson | 2022-01-18 |
| 11196953 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Ofer Shacham | 2021-12-07 |
| 11190718 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein | 2021-11-30 |
| 11153464 | Two dimensional shift array for image processor | Ofer Shacham, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2021-10-19 |
| 11140293 | Sheet generator for image processor | Albert Meixner, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein | 2021-10-05 |
| 11138013 | Energy efficient processor core architecture for image processor | Albert Meixner, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2021-10-05 |
| 10998070 | Shift register with reduced wiring complexity | — | 2021-05-04 |
| 10884959 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2021-01-05 |
| 10872393 | Image processor with high throughput internal communication protocol | Albert Meixner, Qiuling Zhu, Ji Kim, Artem Vasilyev, Ofer Shacham | 2020-12-22 |
| 10861214 | Graphics processor with non-blocking concurrent architecture | Luke T. Peterson, James Alexander McCombe, Steven J. Clohset | 2020-12-08 |
| 10791284 | Virtual linebuffers for image signal processors | Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein, Albert Meixner | 2020-09-29 |
| 10789505 | Convolutional neural network on programmable two dimensional image processor | Ofer Shacham, David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein | 2020-09-29 |
| 10789202 | Image processor with configurable number of active cores and supporting internal network | Albert Meixner, Ji Kim, Ofer Shacham | 2020-09-29 |