Issued Patents All Time
Showing 26–50 of 193 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10783605 | Multistage collector for outputs in multiprocessor systems | James Alexander McCombe, Steven J. Clohset, Luke T. Peterson | 2020-09-22 |
| 10754654 | Energy efficient processor core architecture for image processor | Albert Meixner, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2020-08-25 |
| 10733956 | Macro I/O unit for image processor | Albert Meixner, Neeti Desai, Dilan Manatunga, William R. Mark | 2020-08-04 |
| 10719295 | Circuit to perform dual input value absolute value and sum operation | Artem Vasilyev, Albert Meixner | 2020-07-21 |
| 10719905 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Ofer Shacham, Albert Meixner, Daniel Frederic Finchelstein, David Patterson +4 more | 2020-07-21 |
| 10706006 | Image processor I/O unit | Asif Khan, Neeti Desai, David N. Warren | 2020-07-07 |
| 10685422 | Compiler managed memory for image processor | Albert Meixner, Hyunchul Park, Qiuling Zhu | 2020-06-16 |
| 10638073 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein | 2020-04-28 |
| 10560598 | Sheet generator for image processor | Albert Meixner, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein | 2020-02-11 |
| 10546211 | Convolutional neural network on programmable two dimensional image processor | Ofer Shacham, David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein | 2020-01-28 |
| 10531030 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Ofer Shacham | 2020-01-07 |
| 10516833 | Virtual linebuffers for image signal processors | Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein, Albert Meixner | 2019-12-24 |
| 10503689 | Image processor I/O unit | Asif Khan, Neeti Desai, David N. Warren | 2019-12-10 |
| 10504480 | Macro I/O unit for image processor | Albert Meixner, Neeti Desai, Dilan Manatunga, William R. Mark | 2019-12-10 |
| 10489878 | Configurable and programmable image processor unit | Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more | 2019-11-26 |
| 10481870 | Circuit to perform dual input value absolute value and sum operation | Artem Vasilyev, Albert Meixner | 2019-11-19 |
| 10477164 | Shift register with reduced wiring complexity | — | 2019-11-12 |
| 10417732 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Ofer Shacham, Albert Meixner, Daniel Frederic Finchelstein, David Patterson +4 more | 2019-09-17 |
| 10397450 | Two dimensional shift array for image processor | Ofer Shacham, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2019-08-27 |
| 10380969 | Macro I/O unit for image processor | Albert Meixner, Neeti Desai, Dilan Manatunga, William R. Mark | 2019-08-13 |
| 10334194 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Ofer Shacham | 2019-06-25 |
| 10321077 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein | 2019-06-11 |
| 10313641 | Shift register with reduced wiring complexity | — | 2019-06-04 |
| 10304156 | Compiler managed memory for image processor | Albert Meixner, Hyunchul Park, Qiuling Zhu | 2019-05-28 |
| 10291813 | Sheet generator for image processor | Albert Meixner, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein | 2019-05-14 |