Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020027 | Convolutional neural network on programmable two dimensional image processor | David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein, Jason Redgrave | 2024-06-25 |
| 11250537 | Configurable and programmable image processor unit | Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more | 2022-02-15 |
| 11196953 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave | 2021-12-07 |
| 11190718 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein | 2021-11-30 |
| 11153464 | Two dimensional shift array for image processor | Jason Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2021-10-19 |
| 11140293 | Sheet generator for image processor | Albert Meixner, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein | 2021-10-05 |
| 11138013 | Energy efficient processor core architecture for image processor | Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, Qiuling Zhu | 2021-10-05 |
| 10915773 | Statistics operations on two dimensional image processor | Edward Chang, Daniel Frederic Finchelstein, Szepo Robert Hung, Albert Meixner | 2021-02-09 |
| 10872393 | Image processor with high throughput internal communication protocol | Jason Redgrave, Albert Meixner, Qiuling Zhu, Ji Kim, Artem Vasilyev | 2020-12-22 |
| 10789202 | Image processor with configurable number of active cores and supporting internal network | Jason Redgrave, Albert Meixner, Ji Kim | 2020-09-29 |
| 10791284 | Virtual linebuffers for image signal processors | Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein, Albert Meixner | 2020-09-29 |
| 10789505 | Convolutional neural network on programmable two dimensional image processor | David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein, Jason Redgrave | 2020-09-29 |
| 10754654 | Energy efficient processor core architecture for image processor | Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, Qiuling Zhu | 2020-08-25 |
| 10719905 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, David Patterson +4 more | 2020-07-21 |
| 10638073 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein | 2020-04-28 |
| 10560598 | Sheet generator for image processor | Albert Meixner, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein | 2020-02-11 |
| 10546211 | Convolutional neural network on programmable two dimensional image processor | David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein, Jason Redgrave | 2020-01-28 |
| 10531030 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave | 2020-01-07 |
| 10516833 | Virtual linebuffers for image signal processors | Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein, Albert Meixner | 2019-12-24 |
| 10489878 | Configurable and programmable image processor unit | Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more | 2019-11-26 |
| 10417732 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, David Patterson +4 more | 2019-09-17 |
| 10397450 | Two dimensional shift array for image processor | Jason Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2019-08-27 |
| 10387988 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Albert Meixner, Hyunchul Park, William R. Mark, Daniel Frederic Finchelstein | 2019-08-20 |
| 10387989 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Albert Meixner, Hyunchul Park, William R. Mark, Daniel Frederic Finchelstein | 2019-08-20 |
| 10334194 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave | 2019-06-25 |