Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10321077 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein | 2019-06-11 |
| 10291813 | Sheet generator for image processor | Albert Meixner, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein | 2019-05-14 |
| 10284744 | Sheet generator for image processor | Albert Meixner, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein | 2019-05-07 |
| 10277833 | Virtual linebuffers for image signal processors | Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein, Albert Meixner | 2019-04-30 |
| 10275253 | Energy efficient processor core architecture for image processor | Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, Qiuling Zhu | 2019-04-30 |
| 10216487 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Albert Meixner, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Redgrave | 2019-02-26 |
| 10185560 | Multi-functional execution lane for image processor | Artem Vasilyev, Jason Redgrave, Albert Meixner | 2019-01-22 |
| 10095479 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Albert Meixner, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Redgrave | 2018-10-09 |
| 9986187 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave | 2018-05-29 |
| 9978116 | Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave | 2018-05-22 |
| 9965824 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, David Patterson +4 more | 2018-05-08 |
| 9830150 | Multi-functional execution lane for image processor | Artem Vasilyev, Jason Redgrave, Albert Meixner | 2017-11-28 |
| 9772852 | Energy efficient processor core architecture for image processor | Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, Qiuling Zhu | 2017-09-26 |
| 9769356 | Two dimensional shift array for image processor | Jason Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2017-09-19 |
| 9756268 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein | 2017-09-05 |
| 9749548 | Virtual linebuffers for image signal processors | Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein, Albert Meixner | 2017-08-29 |
| 8966413 | System and method for a chip generator | Mark A. Horowitz, Stephen Richardson | 2015-02-24 |