Issued Patents All Time
Showing 51–75 of 193 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10284744 | Sheet generator for image processor | Albert Meixner, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein | 2019-05-07 |
| 10277833 | Virtual linebuffers for image signal processors | Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein, Albert Meixner | 2019-04-30 |
| 10275253 | Energy efficient processor core architecture for image processor | Albert Meixner, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2019-04-30 |
| 10242426 | Multistage collector for outputs in multiprocessor systems | James Alexander McCombe, Steven J. Clohset, Luke T. Peterson | 2019-03-26 |
| 10216487 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Albert Meixner, Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu | 2019-02-26 |
| 10204396 | Compiler managed memory for image processor | Albert Meixner, Hyunchul Park, Qiuling Zhu | 2019-02-12 |
| 10185560 | Multi-functional execution lane for image processor | Artem Vasilyev, Albert Meixner, Ofer Shacham | 2019-01-22 |
| 10095479 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Albert Meixner, Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu | 2018-10-09 |
| 9986187 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Ofer Shacham | 2018-05-29 |
| 9978116 | Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Ofer Shacham | 2018-05-22 |
| 9965824 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Ofer Shacham, Albert Meixner, Daniel Frederic Finchelstein, David Patterson +4 more | 2018-05-08 |
| 9830150 | Multi-functional execution lane for image processor | Artem Vasilyev, Albert Meixner, Ofer Shacham | 2017-11-28 |
| 9772852 | Energy efficient processor core architecture for image processor | Albert Meixner, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2017-09-26 |
| 9769356 | Two dimensional shift array for image processor | Ofer Shacham, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2017-09-19 |
| 9756268 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein | 2017-09-05 |
| 9749548 | Virtual linebuffers for image signal processors | Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein, Albert Meixner | 2017-08-29 |
| 9665970 | Variable-sized concurrent grouping for multiprocessing | Steven J. Clohset, James Alexander McCombe, Luke T. Peterson | 2017-05-30 |
| 9606176 | Integrated circuit (IC) with primary and secondary networks and device containing such an IC | Marc Miller, Steven Teig, Brad Hutchings, Danny Thom | 2017-03-28 |
| 9595074 | Multistage collector for outputs in multiprocessor systems | James Alexander McCombe, Steven J. Clohset, Luke T. Peterson | 2017-03-14 |
| 9494967 | Trigger circuits and event counters for an IC | Brad Hutchings, Dai Huang, Steven Teig | 2016-11-15 |
| 9489175 | Configurable IC's with large carry chains | Herman Schmit | 2016-11-08 |
| 9466091 | Atomic memory update unit and methods | Steven J. Clohset, Luke T. Peterson | 2016-10-11 |
| 9461650 | User registers implemented with routing circuits in a configurable IC | — | 2016-10-04 |
| 9430811 | Graphics processor with non-blocking concurrent architecture | Luke T. Peterson, James Alexander McCombe, Steven J. Clohset | 2016-08-30 |
| 9407578 | System and method of arbitrating access to interconnect | Joseph M. Richards, Steven J. Clohset | 2016-08-02 |