BP

Binh Pham

IN Intel: 12 patents #3,417 of 30,777Top 15%
Oracle: 4 patents #3,141 of 14,854Top 25%
NV NVIDIA: 1 patents #4,316 of 7,811Top 60%
Overall (All Time): #247,827 of 4,157,543Top 6%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12405770 Matrix transpose and multiply Menachem Adelman, Robert Valentine, Barukh Ziv, Amit Gradstein, Simon Rubanovich +5 more 2025-09-02
11989135 Programmable address range engine for larger region sizes Farah E. FARGO, Mitchell Diamond, David Keppel, Samantika S. Sury, Shobha Vissapragada 2024-05-21
11972230 Matrix transpose and multiply Menachem Adelman, Robert Valentine, Barukh Ziv, Amit Gradstein, Simon Rubanovich +5 more 2024-04-30
11886884 Branch prediction based on coherence operations in processors Christopher B. Wilkerson, Patrick Lu, Jared W. Stark, IV 2024-01-30
11816036 Method and system for performing data movement operations with read snapshot and in place write update Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more 2023-11-14
11370103 Bit driving tool and device for use therewith Alan K. Farrell 2022-06-28
11327894 Method and system for performing data movement operations with read snapshot and in place write update Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more 2022-05-10
11055232 Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBS David Keppel 2021-07-06
10860244 Method and apparatus for multi-level memory early page demotion Christopher B. Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, Zhe Wang 2020-12-08
10754782 Apparatuses, methods, and systems to accelerate store processing Chen DAN 2020-08-25
10606755 Method and system for performing data movement operations with read snapshot and in place write update Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more 2020-03-31
10521236 Branch prediction based on coherence operations in processors Christopher B. Wilkerson, Patrick Lu, Jared W. Stark, IV 2019-12-31
10496551 Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power Ren Wang 2019-12-03
9298868 Hierarchical pushdown of cells and nets to any logical depth Vikas Agrawal, Shrivathsa BHARGAVRAVICHANDRAN, Jay Chen, Sridhar Krishnamurthy, Umang Shah +1 more 2016-03-29
6535968 Apparatus, system, and method for reducing bus contention during consecutive read-write operations 2003-03-18
6256716 Apparatus, system and method for reducing bus contention during consecutive read-write operations 2001-07-03
6119196 System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates Shimon Muller, Curt Berg 2000-09-12
6052738 Method and apparatus in a packet routing switch for controlling access at different data rates to a shared memory Shimon Muller, Curt Berg 2000-04-18