Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10884735 | Instruction and logic for predication and implicit destination | Jamison D. Collins, Sebastian Winkel, Howard H. Chen | 2021-01-05 |
| 10346170 | Performing partial register write operations in a processor | Jamison D. Collins, Sebastian Winkel | 2019-07-09 |
| 10324724 | Hardware apparatuses and methods to fuse instructions | Patrick P. Lai, Tyler Sondag, Sebastian Winkel, Polychronis Xekalakis, Ethan Schuchman | 2019-06-18 |
| 10241801 | Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator | Sergey P. Scherbinin, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more | 2019-03-26 |
| 10241789 | Method to do control speculation on loads in a high performance strand-based loop accelerator | Alexander Y. Ostanevich, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more | 2019-03-26 |
| 10241794 | Apparatus and methods to support counted loop exits in a multi-strand loop processor | Sergey P. Scherbinin, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more | 2019-03-26 |
| 10235171 | Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor | Alexander Y. Ostanevich, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more | 2019-03-19 |
| 10133582 | Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor | Nikolay Kosarev, Sergey Y. Shishlov, Alexander V. Butuzov, Boris A. Babayan, Andrey Kluchnikov | 2018-11-20 |
| 10095623 | Hardware apparatuses and methods to control access to a multiple bank data cache | Andrey Kluchnikov, Sergey Y. Shishlov, Boris A. Babayan | 2018-10-09 |
| 9904546 | Instruction and logic for predication and implicit destination | Jamison D. Collins, Sebastian Winkel, Howard H. Chen | 2018-02-27 |
| 9858226 | Two wire serial voltage identification protocol | Edward R. Stanford, Waseem Kraipak | 2018-01-02 |
| 9811340 | Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor | Nikolay Kosarev, Sergey Y. Shishlov, Andrey Kluchnikov, Alexander V. Butuzov, Boris A. Babayan +2 more | 2017-11-07 |
| 9645819 | Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor | Nikolay Kosarev, Sergey Y. Shishlov, Alexey Y. Sivtsov, Alexander V. Butuzov, Boris A. Babayan +1 more | 2017-05-09 |
| 9632790 | Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order | Nikolay Kosarev, Sergey Y. Shishlov, Alexey Y. Sivtsov, Yuriy V Baida, Alexander V. Butuzov +2 more | 2017-04-25 |
| 9471501 | Hardware apparatuses and methods to control access to a multiple bank data cache | Andrey Kluchnikov, Sergey Y. Shishlov, Boris A. Babayan | 2016-10-18 |
| 8417986 | Time negotiation using serial voltage identification communication | Waseem Kraipak, Edward R. Stanford | 2013-04-09 |
| 8412976 | Data negotiation using serial voltage identification communication | Waseem Kraipak, Edward R. Stanford | 2013-04-02 |