Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10514927 | Instruction and logic for sorting and retiring stores | Anton Lechanka, Andrey Efimov, Andrey Kluchnikov, Kamil Garifullin, Igor Burovenko +1 more | 2019-12-24 |
| 10133582 | Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor | Nikolay Kosarev, Jayesh Iyer, Alexander V. Butuzov, Boris A. Babayan, Andrey Kluchnikov | 2018-11-20 |
| 10095623 | Hardware apparatuses and methods to control access to a multiple bank data cache | Andrey Kluchnikov, Jayesh Iyer, Boris A. Babayan | 2018-10-09 |
| 9811340 | Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor | Nikolay Kosarev, Jayesh Iyer, Andrey Kluchnikov, Alexander V. Butuzov, Boris A. Babayan +2 more | 2017-11-07 |
| 9645819 | Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor | Jayesh Iyer, Nikolay Kosarev, Alexey Y. Sivtsov, Alexander V. Butuzov, Boris A. Babayan +1 more | 2017-05-09 |
| 9632790 | Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order | Jayesh Iyer, Nikolay Kosarev, Alexey Y. Sivtsov, Yuriy V Baida, Alexander V. Butuzov +2 more | 2017-04-25 |
| 9529596 | Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits | Boris A. Babayan, Vladimir Pentkovski, Alexander V. Butuzov, Alexey Y. Sivtsov, Nikolay Kosarev | 2016-12-27 |
| 9471501 | Hardware apparatuses and methods to control access to a multiple bank data cache | Andrey Kluchnikov, Jayesh Iyer, Boris A. Babayan | 2016-10-18 |