Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10579378 | Instructions for manipulating a multi-bit predicate register for predicating instruction sequences | Edward T. Grochowski, Victor W. Lee, Sergey A. Rozhkov | 2020-03-03 |
| 10514927 | Instruction and logic for sorting and retiring stores | Anton Lechanka, Andrey Efimov, Sergey Y. Shishlov, Andrey Kluchnikov, Kamil Garifullin +1 more | 2019-12-24 |
| 10241789 | Method to do control speculation on loads in a high performance strand-based loop accelerator | Alexander Y. Ostanevich, Sergey P. Scherbinin, Jayesh Iyer, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-26 |
| 10241794 | Apparatus and methods to support counted loop exits in a multi-strand loop processor | Sergey P. Scherbinin, Jayesh Iyer, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-26 |
| 10241801 | Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator | Jayesh Iyer, Sergey P. Scherbinin, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-26 |
| 10235171 | Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor | Alexander Y. Ostanevich, Jayesh Iyer, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-19 |
| 10133582 | Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor | Nikolay Kosarev, Sergey Y. Shishlov, Jayesh Iyer, Alexander V. Butuzov, Andrey Kluchnikov | 2018-11-20 |
| 10095623 | Hardware apparatuses and methods to control access to a multiple bank data cache | Andrey Kluchnikov, Jayesh Iyer, Sergey Y. Shishlov | 2018-10-09 |
| 9811340 | Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor | Nikolay Kosarev, Jayesh Iyer, Sergey Y. Shishlov, Andrey Kluchnikov, Alexander V. Butuzov +2 more | 2017-11-07 |
| 9645819 | Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor | Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexey Y. Sivtsov, Alexander V. Butuzov +1 more | 2017-05-09 |
| 9529596 | Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits | Vladimir Pentkovski, Alexander V. Butuzov, Sergey Y. Shishlov, Alexey Y. Sivtsov, Nikolay Kosarev | 2016-12-27 |
| 9471501 | Hardware apparatuses and methods to control access to a multiple bank data cache | Andrey Kluchnikov, Jayesh Iyer, Sergey Y. Shishlov | 2016-10-18 |