| 10241789 |
Method to do control speculation on loads in a high performance strand-based loop accelerator |
Alexander Y. Ostanevich, Sergey P. Scherbinin, Jayesh Iyer, Dmitry M. Maslennikov, Denis G. Motin +3 more |
2019-03-26 |
| 10241794 |
Apparatus and methods to support counted loop exits in a multi-strand loop processor |
Sergey P. Scherbinin, Jayesh Iyer, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin +3 more |
2019-03-26 |
| 10241801 |
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator |
Jayesh Iyer, Sergey P. Scherbinin, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin +3 more |
2019-03-26 |
| 10235171 |
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor |
Alexander Y. Ostanevich, Jayesh Iyer, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin +3 more |
2019-03-19 |
| 7069412 |
Method of using a plurality of virtual memory spaces for providing efficient binary compatibility between a plurality of source architectures and a single target architecture |
Boris A. Babaian, Roman A. Khvatov |
2006-06-27 |