Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9625093 | Portable drip containment device apparatus and method | — | 2017-04-18 |
| 8931658 | Portable drip containment device apparatus and method | — | 2015-01-13 |
| 8740006 | Portable drip containment device apparatus and method | — | 2014-06-03 |
| 8702849 | Dust screen and method for dry bulk storage units | — | 2014-04-22 |
| 8479946 | Portable drip containment device apparatus and method | — | 2013-07-09 |
| 8467837 | MAC controlled sleep mode/wake-up mode with staged wake-up for power management | Bruce E. Edwards | 2013-06-18 |
| 8275423 | MAC controlled sleep mode/wake-up mode with staged wake-up for power management devices | Bruce E. Edwards | 2012-09-25 |
| 7702371 | Low-power mode clock management for wireless communication devices | Bruce E. Edwards | 2010-04-20 |
| 7583985 | MAC controlled sleep mode/wake-up mode with staged wake-up for power management | Bruce E. Edwards | 2009-09-01 |
| 7200379 | Low-power mode clock management for wireless communication devices | Bruce E. Edwards | 2007-04-03 |
| 7043516 | Reduction of add-pipe logic by operand offset shift | Gilbert M. Wolrich, John D. Clouser | 2006-05-09 |
| 6779012 | Computer method and apparatus for division and square root operations using signed digit | Robert J. Dupcak, Jonathan Krause, Sridhar Samudrala | 2004-08-17 |
| 6653869 | Universal CMOS single input, low swing sense amplifier without reference voltage | Robert J. Dupcak, Randy L. Allmon | 2003-11-25 |
| 6564239 | Computer method and apparatus for division and square root operations using signed digit | Robert J. Dupcak, Jonathan Krause, Sridhar Samudrala | 2003-05-13 |
| 6480036 | Settable digital CMOS differential sense amplifier | Daniel W. Bailey | 2002-11-12 |
| 6414520 | Universal CMOS single input, low swing sense amplifier without reference voltage | Robert J. Dupcak, Randy L. Allmon | 2002-07-02 |
| 6400186 | Settable digital CMOS differential sense amplifier | Daniel W. Bailey | 2002-06-04 |
| 6366942 | Method and apparatus for rounding floating point results in a digital processing system | Roy Badeau, William R. Grundmann, Sridhar Samudrala | 2002-04-02 |
| 6360241 | Computer method and apparatus for division and square root operations using signed digit | Robert J. Dupcak, Jonathan Krause, Sridhar Samudrala | 2002-03-19 |
| 6144228 | Generalized push-pull cascode logic technique | Sridhar Samudrala, Robert J. Dupcak | 2000-11-07 |
| 6084455 | High-speed CMOS latch | — | 2000-07-04 |
| 6018756 | Reduced-latency floating-point pipeline using normalization shifts of both operands | Gilbert M. Wolrich, John D. Clouser | 2000-01-25 |