Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10528473 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella +3 more | 2020-01-07 |
| 9940686 | Exploiting frame to frame coherency in a sort-middle architecture | Juan Fernandez, Pedro Marcuello, Tomas G. Akenine-Moller | 2018-04-10 |
| 9922393 | Exploiting frame to frame coherency in a sort-middle architecture | Juan Fernandez, Pedro Marcuello, Tomas G. Akenine-Moller | 2018-03-20 |
| 9904977 | Exploiting frame to frame coherency in a sort-middle architecture | Juan Fernandez, Pedro Marcuello, Tomas G. Akenine-Moller | 2018-02-27 |
| 9374542 | Image signal processor with a block checking circuit | Kyriakos A. Stavrou, Pedro Marcuello, Grigorios Magklis, Juan Fernandez, Carlos Madriles +2 more | 2016-06-21 |
| 9286172 | Fault-aware mapping for shared last level cache (LLC) | Tanausu Ramirez, Enric Herrero, Matteo Monchiero, Xavier Vera | 2016-03-15 |
| 9176895 | Increased error correction for cache memories through adaptive replacement policies | Xavier Vera, Enric Herrero Abellanas, Daniel Sanchez, Nicholas Axelos, Tanausu Ramirez | 2015-11-03 |
| 9112537 | Content-aware caches for reliability | Tanausu Ramirez, Enric Herrero, Matteo Monchiero, Xavier Vera | 2015-08-18 |
| 9043659 | Banking of reliability metrics | Enric Herrero Abellanas, Xavier Vera, Tanausu Ramirez, Nicholas Axelos, Daniel Sanchez | 2015-05-26 |