Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9158693 | Dynamically controlling cache size to maximize energy efficiency | Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman +1 more | 2015-10-13 |
| 9152205 | Mechanism for facilitating faster suspend/resume operations in computing systems | Ohad Falik, Eliezer Weissmann, Michael Mishaeli, Nadav Shulman, Robert E. Gough +3 more | 2015-10-06 |
| 9141180 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2015-09-22 |
| 9122464 | Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode | Inder M. Sodhi, Efraim Rotem, Sanjeev Jahagirdar, Varghese George | 2015-09-01 |
| 9098261 | User level control of power management policies | Krishnakanth V. Sistla, Jeremy J. Shrall, Stephen H. Gunther, Efraim Rotem, Eliezer Weissmann +7 more | 2015-08-04 |
| 9092210 | Controlling current transients in a processor | Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Eliezer Weissmann +1 more | 2015-07-28 |
| 9081687 | Method and apparatus for MONITOR and MWAIT in a distributed cache architecture | Zeev Offen, Iris Sorani | 2015-07-14 |
| 9075614 | Managing power consumption in a multi-core processor | Eric Fetzer, Reid James Riedlinger, Don Soltis, William J. Bowhill, Satish Shrimali +5 more | 2015-07-07 |
| 9074947 | Estimating temperature of a processor core in a low power state without thermal sensor information | Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan +1 more | 2015-07-07 |
| 9075610 | Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation | Eliezer Weissmann, Efraim Rotem, Avinash N. Ananthakrishnan, Hisham Abu Salah, Nadav Shulman | 2015-07-07 |
| 9069555 | Managing power consumption in a multi-core processor | Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali +5 more | 2015-06-30 |
| 9063729 | Device, system and method of generating an execution instruction based on a memory-access instruction | Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov | 2015-06-23 |
| 9026829 | Package level power state optimization | Eliezer Weissmann, Nadav Shulman, Hisham Abu Salah, Dan Baum | 2015-05-05 |
| 8996895 | Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates | Eliezer Weissmann, Ofer Nathan, Nadav Shulman | 2015-03-31 |
| 8819461 | Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply | Inder M. Sodhi, Michael Zelikson, Sanjeev Jahagirdar, Varghese George | 2014-08-26 |
| 8799687 | Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates | Eliezer Weissmann, Ofer Nathan, Nadav Shulman | 2014-08-05 |
| 8726048 | Power management coordination in multi-core processors | Efraim Rotem, Eliezer Weissmann | 2014-05-13 |
| 8707062 | Method and apparatus for powered off processor core mode | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2014-04-22 |
| 8650424 | Method and apparatus to control power consumption of a plurality of processor cores | Efraim Rotem, Oren Lamdan | 2014-02-11 |
| 8508073 | Simultaneous multi-voltage rail voltage regulation messages | Hung-Piao Ma, Gil Schwarzband, Annabelle Pratt, Jorge P. Rodriguez, Joseph T. DiBene, II +3 more | 2013-08-13 |
| 8281083 | Device, system and method of generating an execution instruction based on a memory-access instruction | Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov | 2012-10-02 |
| 8222766 | Simultaneous multi-voltage rail voltage regulation messages | Hung-Piao Ma, Gil Schwarzband, Annabelle Pratt, Jorge P. Rodriguez, Joseph T. DiBene, II +3 more | 2012-07-17 |
| 8166320 | Power aware software pipelining for hardware accelerators | Ron Gabor, Hong Jiang, Doron Rajwan, James Varga, Gady Yearim +1 more | 2012-04-24 |
| 7966511 | Power management coordination in multi-core processors | Efraim Rotem, Eliezer Weissmann | 2011-06-21 |
| 7962771 | Method, system, and apparatus for rerouting interrupts in a multi-core processor | Justin J. Song, Devadatta V. Bodas, Ohad Falik, Ilan Pardo, Anil Aggarwal +2 more | 2011-06-14 |