Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367926 | Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays | Gururaj K. Shamanna, Naveen Kumar M., Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen, Sravan K. Puchakayala | 2025-07-22 |
| 12141890 | Enabling product SKUs based on chiplet configurations | Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2024-11-12 |
| 12112398 | Disaggregation of system-on-chip (SOC) architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2024-10-08 |
| 12056789 | Disaggregation of system-on-chip (SOC) architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2024-08-06 |
| 11908542 | Energy efficient memory array with optimized burst read and write data access | Charles Augustine, Somnath Paul, Turbo Majumder, Andrew Lines, Altug Koker +2 more | 2024-02-20 |
| 11874715 | Dynamic power budget allocation in multi-processor system | Nikos Kaburlasos, Bhushan M. Borole, Kamal Sinha, Sanjeev Jahagirdar | 2024-01-16 |
| 11763416 | Disaggregation of system-on-chip (SOC) architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2023-09-19 |
| 11756150 | Disaggregation of system-on-chip (SOC) architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2023-09-12 |
| 11493974 | Dynamic power budget allocation in multi-processor system | Nikos Kaburlasos, Bhushan M. Borole, Kamal Sinha, Sanjeev Jahagirdar | 2022-11-08 |
| 11410266 | Disaggregation of System-On-Chip (SOC) architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2022-08-09 |
| 11386521 | Enabling product SKUS based on chiplet configurations | Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2022-07-12 |
| 11176990 | System, apparatus and method for segmenting a memory array | Bhushan M. Borole, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhishek R. Appu | 2021-11-16 |
| 10909652 | Enabling product SKUs based on chiplet configurations | Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2021-02-02 |
| 10817012 | System, apparatus and method for providing a local clock signal for a memory array | Altug Koker, Bhushan M. Borole, Kamal Sinha, Abhishek R. Appu, Anupama A. Thaploo +2 more | 2020-10-27 |
| 10803548 | Disaggregation of SOC architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2020-10-13 |
| 10790010 | System, apparatus and method for segmenting a memory array | Bhushan M. Borole, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu | 2020-09-29 |
| 10754809 | Reducing aging of register file keeper circuits | Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Altug Koker, Abhishek R. Appu +2 more | 2020-08-25 |
| 10747286 | Dynamic power budget allocation in multi-processor system | Nikos Kaburlasos, Bhushan M. Borole, Kamal Sinha, Sanjeev Jahagirdar | 2020-08-18 |
| 10491217 | Low-power clock gate circuit | Steven Hsu, Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2019-11-26 |
| 10409319 | System, apparatus and method for providing a local clock signal for a memory array | Altug Koker, Bhushan M. Borole, Kamal Sinha, Abhishek R. Appu, Anupama A. Thaploo +2 more | 2019-09-10 |
| 10347324 | System, apparatus and method for segmenting a memory array | Bhushan M. Borole, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu | 2019-07-09 |
| 10333379 | Power switching circuitry including power-up control | Suphachai Chai Sutanthavibul, Anupama A. Thaploo, Surya Sasi Kiran Tallapragada, Daivik H Bhatt, Lei Jiang +3 more | 2019-06-25 |
| 10324721 | Reducing aging of register file keeper circuits | Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Altug Koker, Abhishek R. Appu +2 more | 2019-06-18 |
| 10193536 | Shared keeper and footer flip-flop | Amit Agarwal, Steven Hsu, Simeon Realov, Ram Krishnamurthy | 2019-01-29 |
| 10177765 | Integrated clock gate circuit with embedded NOR | Steven Hsu, Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2019-01-08 |