Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367926 | Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays | Naveen Kumar M., Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen, Sravan K. Puchakayala, Iqbal Rajwani | 2025-07-22 |
| 11927982 | Keeper-free integrated clock gate circuit | Naveen Kumar M, Harishankar Sahu, Abhishek Chouksey, Madhusudan Rao | 2024-03-12 |
| 10996709 | Low power clock gate circuit | Mitesh Goyal, Jagadeesh Chandra Salaka, Purna C. Nayak, Abhishek A. Sharma, Harishankar Sahu | 2021-05-04 |
| 10269417 | Apparatus for adaptive write assist for memory | Stefan Rusu, Eric A. Karl, Zheng Guo | 2019-04-23 |
| 10140044 | Efficient memory bank design | Priyankar Mathuria, Rakesh Sinha | 2018-11-27 |
| 9921630 | Apparatus and method for reducing leakage power of a circuit | Stefan Rusu, Phani Kumar Kandula, Sankalan Prasad, Mandar R. Ranade, Narayanan Natarajan +1 more | 2018-03-20 |
| 9570158 | Output latch for accelerated memory access | Priyankar Mathuria, VRC Krishna Teja Kunisetty | 2017-02-14 |
| 9207750 | Apparatus and method for reducing leakage power of a circuit | Stefan Rusu, Phani Kumar Kandula, Sankalan Prasad, Mandar R. Ranade, Narayanan Natarajan +1 more | 2015-12-08 |
| 6321297 | Avoiding tag compares during writes in multi-level cache hierarchy | Chih-Hung Chung, Derek T. Bachand | 2001-11-20 |