Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11782181 | Data fusion enhanced multi-modality wellbore integrity inspection system | Ansas Matthias Kasten, Yuri Alexeyevich Plotnikov, Sarah Lillian Katz, Frederick Wilson Wheeler, William Robert Ross +1 more | 2023-10-10 |
| 10634890 | Miniaturized microscope for phase contrast and multicolor fluorescence imaging | Ansas Matthias Kasten, William Albert Challener, Jason Harris Karp | 2020-04-28 |
| 10400574 | Apparatus and method for inspecting integrity of a multi-barrier wellbore | Ansas Matthias Kasten, Juan Pablo Cilia, John Scott Price, William Robert Ross, Chengbao Wang | 2019-09-03 |
| 10393532 | Emergency responsive navigation | Eric A. Foreman | 2019-08-27 |
| 10304763 | Producing wafer level packaging using leadframe strip and related device | Richard S. Graf, Kibby B. Horsford | 2019-05-28 |
| 10249590 | Stacked dies using one or more interposers | Sebastian T. Ventrone, Richard S. Graf | 2019-04-02 |
| 10208587 | System and method for monitoring integrity of a wellbore | Ansas Matthias Kasten, John Scott Price, Juan Pablo Cilia, Chengbao Wang, William Robert Ross +2 more | 2019-02-19 |
| 10170224 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Richard S. Graf | 2019-01-01 |
| 10120102 | Fluid sensor cable assembly, system, and method | Loucas Tsakalakos, Slawomir Rubinsztajn, Renato Guida, Mahadevan Balasubramaniam, Boon Kwee Lee +3 more | 2018-11-06 |
| 10049570 | Controlling right-of-way for priority vehicles | Eric A. Foreman | 2018-08-14 |
| 10043962 | Thermoelectric cooling using through-silicon vias | Richard S. Graf | 2018-08-07 |
| 10013519 | Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation | Jeanne P. Bickford | 2018-07-03 |
| 9952500 | Adjusting of patterns in design layout for optical proximity correction | Arun Sankar Mampazhy | 2018-04-24 |
| 9941458 | Integrated circuit cooling using embedded peltier micro-vias in substrate | Jeffrey P. Gambino, Richard S. Graf | 2018-04-10 |
| 9913405 | Glass interposer with embedded thermoelectric devices | Jeffrey P. Gambino, Richard S. Graf, David J. Russell | 2018-03-06 |
| 9892999 | Producing wafer level packaging using leadframe strip and related device | Richard S. Graf, Kibby B. Horsford | 2018-02-13 |
| 9870851 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Richard S. Graf | 2018-01-16 |
| 9871020 | Through silicon via sharing in a 3D integrated circuit | Sebastian T. Ventrone | 2018-01-16 |
| 9869607 | Systems and methods for distributed measurement | Susanne Madeline Lee, Sachin Narahari Dekate, Majid Nayeri | 2018-01-16 |
| 9865674 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Richard S. Graf | 2018-01-09 |
| 9585257 | Method of forming a glass interposer with thermal vias | Jeffrey P. Gambino, Richard S. Graf, David J. Russell | 2017-02-28 |
| 9569571 | Method and system for timing violations in a circuit | Jeanne P. Bickford, Eric A. Foreman, Kerim Kalafala, Shashank B. Sreekanta | 2017-02-14 |
| 9559283 | Integrated circuit cooling using embedded peltier micro-vias in substrate | Jeffrey P. Gambino, Richard S. Graf | 2017-01-31 |
| 9536732 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Richard S. Graf | 2017-01-03 |
| 9496234 | Wafer-level chip-scale package structure utilizing conductive polymer | Richard S. Graf, Kibby B. Horsford | 2016-11-15 |