Issued Patents All Time
Showing 51–75 of 112 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7851923 | Low resistance and inductance backside through vias and methods of fabricating same | Mete Erturk, Robert A. Groves, Jeffrey B. Johnson, Alvin J. Joseph, Qizhi Liu +1 more | 2010-12-14 |
| 7824961 | Stacked imager package | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce +1 more | 2010-11-02 |
| 7820521 | Conductive through via structure and process for electronic device carriers | Paul S. Andry, Chirag S. Patel, Cornelia K. Tsang | 2010-10-26 |
| 7791168 | Techniques for providing decoupling capacitance | Raymond R. Horton, John U. Knickerbocker, Cornelia K. Tsang | 2010-09-07 |
| 7786596 | Hermetic seal and reliable bonding structures for 3D applications | Kuan-Neng Chen, Bruce K. Furman, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman +1 more | 2010-08-31 |
| 7781781 | CMOS imager array with recessed dielectric | James W. Adkisson, Jeffrey P. Gambino, Zhong-Xiang He, Mark D. Jaffe, Robert K. Leidy +2 more | 2010-08-24 |
| 7768005 | Physically highly secure multi-chip assembly | Vincenzo Condorelli, Claudius Feger, Kevin C. Gotze, Nihad Hadzic, John U. Knickerbocker | 2010-08-03 |
| 7741231 | Techniques for providing decoupling capacitance | Raymond R. Horton, John U. Knickerbocker, Cornelia K. Tsang | 2010-06-22 |
| 7741722 | Through-wafer vias | Paul S. Andry, Kenneth J. Stein, Timothy D. Sullivan, Cornelia K. Tsang, Ping-Chuan Wang +1 more | 2010-06-22 |
| 7722446 | System and device for thinning wafers that have contact bumps | Timothy C. Krywanczyk | 2010-05-25 |
| 7719118 | Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe | 2010-05-18 |
| 7700410 | Chip-in-slot interconnect for 3D chip stacks | Kerry Bernstein, Timothy J. Dalton, Anthony K. Stamper, Richard Q. Williams | 2010-04-20 |
| 7691669 | Techniques for providing decoupling capacitance | Raymond R. Horton, John U. Knickerbocker, Cornelia K. Tsang | 2010-04-06 |
| 7683478 | Hermetic seal and reliable bonding structures for 3D applications | Kuan-Neng Chen, Bruce K. Furman, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman +1 more | 2010-03-23 |
| 7678696 | Method of making through wafer vias | Paul S. Andry, Cornelia K. Tsang | 2010-03-16 |
| 7645701 | Silicon-on-insulator structures for through via in silicon carriers | Brent A. Anderson, Paul S. Andry, Cornelia K. Tsang | 2010-01-12 |
| 7563714 | Low resistance and inductance backside through vias and methods of fabricating same | Mete Erturk, Robert A. Groves, Jeffrey B. Johnson, Alvin J. Joseph, Qizhi Liu +1 more | 2009-07-21 |
| 7557597 | Stacked chip security | Brent A. Anderson | 2009-07-07 |
| 7521798 | Stacked imager package | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce +1 more | 2009-04-21 |
| 7498236 | Silicon wafer thinning end point method | Steven R. Codding, Timothy C. Krywanczyk | 2009-03-03 |
| 7488624 | Techniques for providing decoupling capacitance | Raymond R. Horton, John U. Knickerbocker, Cornelia K. Tsang | 2009-02-10 |
| 7488680 | Conductive through via process for electronic device carriers | Paul S. Andry, Chirag S. Patel, Cornelia K. Tsang | 2009-02-10 |
| 7474104 | Wafer-to-wafer alignments | Thomas Joseph Dalton, Jeffrey P. Gambino, Mark David Jaffee, Stephen E. Luce | 2009-01-06 |
| 7462509 | Dual-sided chip attached modules | Kerry Bernstein, Timothy J. Dalton, Timothy H. Daubenspeck, Jeffrey P. Gambino, Mark D. Jaffe +3 more | 2008-12-09 |
| 7449067 | Method and apparatus for filling vias | Paul S. Andry, Jon A. Casey, Raymond R. Horton, Chiraq S. Patel, Brian R. Sundlof | 2008-11-11 |