Issued Patents All Time
Showing 76–100 of 112 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7435627 | Techniques for providing decoupling capacitance | Raymond R. Horton, John U. Knickerbocker, Cornelia K. Tsang | 2008-10-14 |
| 7402442 | Physically highly secure multi-chip assembly | Vincenzo Condorelli, Claudius Feger, Kevin C. Gotze, Nihad Hadzic, John U. Knickerbocker | 2008-07-22 |
| 7361581 | High surface area aluminum bond pad for through-wafer connections to an electronic package | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard J. Rassel | 2008-04-22 |
| 7361989 | Stacked imager package | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce +1 more | 2008-04-22 |
| 7348210 | Post bump passivation for soft error protection | Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter | 2008-03-25 |
| 7348216 | Rework process for removing residual UV adhesive from C4 wafer surfaces | Steven R. Codding, Timothy C. Krywanczyk, Jocelyn Sylvestre, Matthew R. Whalen | 2008-03-25 |
| 7310036 | Heat sink for integrated circuit devices | Douglas D. Coolbaugh, Ebenezer E. Eshun, Terence B. Hook, Robert M. Rassel, Anthony K. Stamper +1 more | 2007-12-18 |
| 7276787 | Silicon chip carrier with conductive through-vias and method for fabricating same | Daniel C. Edelstein, Paul S. Andry, Leena Paivikki Buchwalter, Jon A. Casey, Sherif A. Goma +9 more | 2007-10-02 |
| 7193423 | Wafer-to-wafer alignments | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Stephen E. Luce | 2007-03-20 |
| 7189595 | Method of manufacture of silicon based package and devices manufactured thereby | John Harold Magerlein, Chirag S. Patel, Herbert I. Stoller | 2007-03-13 |
| 7135124 | Method for thinning wafers that have contact bumps | Timothy C. Krywanczyk | 2006-11-14 |
| 7067914 | Dual chip stack method for electro-static discharge protection of integrated circuits | John C. Malinowski, Steven H. Voldman | 2006-06-27 |
| 7052925 | Method for manufacturing self-compensating resistors within an integrated circuit | William J. Murphy, Anthony K. Stamper, Erick G. Walton | 2006-05-30 |
| 6963132 | Integrated semiconductor device having co-planar device surfaces | Mark C. Hakey, Steven J. Holmes, David V. Horak, Harold G. Linde | 2005-11-08 |
| 6949458 | Self-aligned contact areas for sidewall image transfer formed conductors | Edward W. Conrad, Chung H. Lam, Dale W. Martin | 2005-09-27 |
| 6727118 | Power distribution design method for stacked flip-chip packages | Jerome B. Lasky, Edward J. Nowak | 2004-04-27 |
| 6661100 | Low impedance power distribution structure for a semiconductor chip package | Brent A. Anderson, Randolph F. Knarr, Sarah H. Knickerbocker, Kamalesh K. Srivastava | 2003-12-09 |
| 6642080 | Chip-on-chip interconnections of varied characterstics | Thomas G. Ference, Wayne J. Howell | 2003-11-04 |
| 6635970 | Power distribution design method for stacked flip-chip packages | Jerome B. Lasky, Edward J. Nowak | 2003-10-21 |
| 6627477 | Method of assembling a plurality of semiconductor devices having different thickness | Mark C. Hakey, Steven J. Holmes, David V. Horak, Harold G. Linde | 2003-09-30 |
| 6566759 | Self-aligned contact areas for sidewall image transfer formed conductors | Edward W. Conrad, Chung H. Lam, Dale W. Martin | 2003-05-20 |
| 6507115 | Multi-chip integrated circuit module | Harm Peter Hofstee, Robert K. Montoye | 2003-01-14 |
| 6452265 | Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Rosemary A. Previti-Kelly | 2002-09-17 |
| 6429045 | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, H. Bernhard Pogge +1 more | 2002-08-06 |
| 6294406 | Highly integrated chip-on-chip packaging | Claude L. Bertin, Thomas G. Ference, Wayne J. Howell | 2001-09-25 |