Issued Patents All Time
Showing 26–50 of 112 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8558345 | Integrated decoupling capacitor employing conductive through-substrate vias | Tae Hong Kim, Michael F. McAllister, Michael J. Shapiro | 2013-10-15 |
| 8492816 | Deep trench decoupling capacitor | James S. Nakos, Anthony K. Stamper | 2013-07-23 |
| 8440544 | CMOS structure and method of manufacture | Paul S. Andry, Cornelia K. Tsang | 2013-05-14 |
| 8298917 | Process for wet singulation using a dicing singulation structure | Paul S. Andry, Timothy H. Daubenspeck, Jeffrey P. Gambino, Cornelia K. Tsang | 2012-10-30 |
| 8263497 | High-yield method of exposing and contacting through-silicon vias | Paul S. Andry, John M. Cotte, Michael F. Lofaro, James A. Tornello, Cornelia K. Tsang | 2012-09-11 |
| 8264078 | Metal wiring structures for uniform current density in C4 balls | Timothy H. Daubenspeck, Wolfgang Sauter, Timothy D. Sullivan, Steven L. Wright | 2012-09-11 |
| 8242591 | Electrostatic chucking of an insulator handle substrate | Paul S. Andry, Edward C. Cooney, III, Anthony K. Stamper, Cornelia K. Tsang | 2012-08-14 |
| 8230586 | Method of cooling a resistor | Douglas D. Coolbaugh, Ebenezer E. Eshun, Terence B. Hook, Robert M. Rassel, Anthony K. Stamper +1 more | 2012-07-31 |
| 8198734 | Silicon-on-insulator structures for through via in silicon carriers | Brent A. Anderson, Paul S. Andry, Cornelia K. Tsang | 2012-06-12 |
| 8187923 | Laser release process for very thin Si-carrier build | Paul S. Andry, Leena Paivikki Buchwalter, Matthew J. Farinelli, Sherif A. Goma, Raymond R. Horton | 2012-05-29 |
| 8166651 | Through wafer vias with dishing correction methods | Peter J. Lindgren, Anthony K. Stamper | 2012-05-01 |
| 8138036 | Through silicon via and method of fabricating same | Paul S. Andry, Cornelia K. Tsang | 2012-03-20 |
| 8136084 | Arranging through silicon vias in IC layout | Donald R. Dean, Jr., Peter J. Lindgren, Glen L. Miles, Anthony K. Stamper | 2012-03-13 |
| 8097492 | Method and manufacture of silicon based package and devices manufactured thereby | John Harold Magerlein, Chirag S. Patel, Herbert I. Stoller | 2012-01-17 |
| 8084858 | Metal wiring structures for uniform current density in C4 balls | Timothy H. Daubenspeck, Wolfgang Sauter, Timothy D. Sullivan, Steven L. Wright | 2011-12-27 |
| 8039356 | Through silicon via lithographic alignment and registration | Russell T. Herrin, Peter J. Lindgren, Anthony K. Stamper | 2011-10-18 |
| 8004289 | Wafer-to-wafer alignments | Thomas Joseph Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Stephen E. Luce | 2011-08-23 |
| 7994895 | Heat sink for integrated circuit devices | Douglas D. Coolbaugh, Ebenezer E. Eshun, Terence B. Hook, Robert M. Rassel, Anthony K. Stamper +1 more | 2011-08-09 |
| 7964967 | High surface area aluminum bond pad for through-wafer connections to an electronic package | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard J. Rassel | 2011-06-21 |
| 7932614 | Method of thinning a semiconductor substrate | Steven R. Codding, Timothy C. Krywanczyk, Timothy E. Neary | 2011-04-26 |
| 7898063 | Through substrate annular via including plug filler | Peter J. Lindgren, Anthony K. Stamper, Kenneth J. Stein | 2011-03-01 |
| 7867876 | Method of thinning a semiconductor substrate | Steven R. Codding, Timothy C. Krywanczyk, Timothy E. Neary | 2011-01-11 |
| 7863734 | Dual-sided chip attached modules | Kerry Bernstein, Timothy J. Dalton, Timothy H. Daubenspeck, Jeffrey P. Gambino, Mark D. Jaffe +3 more | 2011-01-04 |
| 7859114 | IC chip and design structure with through wafer vias dishing correction | Peter J. Lindgren, Anthony K. Stamper | 2010-12-28 |
| 7855442 | Silicon based package | John Harold Magerlein, Chirag S. Patel, Herbert I. Stoller | 2010-12-21 |