Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9397042 | Integrated helical multi-layer inductor structures | Thomas J. Brunschwiler, Michele Castriotta, Stefano S. Oggioni, Gerd Schlottig | 2016-07-19 |
| 9111933 | Stacked through-silicon via (TSV) transformer structure | Gary Dale Carpenter, Alan J. Drake, Michael J. Shapiro, Edmund J. Sprogis | 2015-08-18 |
| 9105627 | Coil inductor for on-chip or on-chip stack | Michael J. Shapiro, Gary Dale Carpenter, Alan J. Drake, Edmund J. Sprogis | 2015-08-11 |
| 8943456 | Layout determining for wide wire on-chip interconnect lines | David Goren, Sue Ellen Strang, Kurt A. Tallman, Youri V. Tretiakov | 2015-01-27 |
| 8793637 | Method and system for design and modeling of vertical interconnects for 3DI applications | David Goren | 2014-07-29 |
| 8448119 | Method and system for design and modeling of vertical interconnects for 3DI applications | David Goren | 2013-05-21 |
| 8347244 | Topologies and methodologies for AMS integrated circuit design | Amir Alon, David Goren, Betty Livshitz, Sherman Anatoly, Michael Zelikson | 2013-01-01 |
| 8271913 | Method and system for design and modeling of transmission lines | Roi Carmon, David Goren, Shlomo Shlafman | 2012-09-18 |
| 8056043 | Capacitance modeling | David Goren | 2011-11-08 |
| 8041546 | Capacitance modeling | David Goren | 2011-10-18 |
| 7797662 | Method and system for design and modeling of transmission lines | Roi Carmon, David Goren, Shlomo Shlafman | 2010-09-14 |
| 7454733 | Interconnect-aware methodology for integrated circuit design | Amir Alon, David Goren, Betty Livshitz, Anatoly Sherman, Michael Zelikson | 2008-11-18 |
| 7392490 | System and method of modelling capacitance of on-chip coplanar transmission line structures over a substrate | David Goren | 2008-06-24 |
| 7080340 | Interconnect-aware integrated circuit design | David Goren, Michael Zelikson | 2006-07-18 |