Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9406562 | Integrated circuit and design structure having reduced through silicon via-induced stress | Jeffrey P. Bonn, Brian L. Kinsman, Robert M. Rassel, Edmund J. Sprogis, Daniel S. Vanslette | 2016-08-02 |
| 8954901 | Parameter variation improvement | Pavan Y. Bashaboina, Howard S. Landis | 2015-02-10 |