Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6974722 | Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules | Glenn G. Daves, Jason L. Frankel, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero +1 more | 2005-12-13 |
| 6762489 | Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules | Glenn G. Daves, Jason L. Frankel, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero +1 more | 2004-07-13 |
| 6469375 | High bandwidth 3D memory packaging technique | William F. Beausoleil, Edmund Blackshear, Michael J. Ellsworth, Jr., Norton J. Tomassetti | 2002-10-22 |
| 6459160 | Package with low stress hermetic seal | Lewis S. Goldmann, Eric D. Perfecto, Raed A. Sherif, Hilton T. Toy | 2002-10-01 |
| 6442041 | MCM—MLC technology | Simone Rehm, Bernd Garden, Erich Klink, Gisbert Thomke | 2002-08-27 |
| 6342407 | Low stress hermetic seal | Lewis S. Goldmann, Eric D. Perfecto, Raed A. Sherif, Hilton T. Toy | 2002-01-29 |
| 6043724 | Two-stage power noise filter with on and off chip capacitors | Roland Frech, Erich Klink, Ulrich Weiss, Thomas-Michael Winkel | 2000-03-28 |
| 5914533 | Multilayer module with thinfilm redistribution area | Roland Frech, Hubert Harrer, Erich Klink | 1999-06-22 |
| 5032897 | Integrated thermoelectric cooling | Mohanlal S. Mansuria, Joseph M. Mosley, Richard D. Musa, Vito J. Tuozzolo | 1991-07-16 |
| 4718039 | Intermediate memory array with a parallel port and a buffered serial port | Frederick J. Aichelmann, Jr., Vincent F. Sollitto, Jr. | 1988-01-05 |