Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11342697 | Dual-level pad card edge self-guide and alignment of connector | Paul W. Coteus, Thomas M. Cipolla, Kyu-hyoun Kim | 2022-05-24 |
| 10813215 | Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance | Jean Audet, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada | 2020-10-20 |
| 10806030 | Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance | Jean Audet, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada | 2020-10-13 |
| 10748852 | Multi-chip module (MCM) with chip-to-chip connection redundancy and method | Wolfgang Sauter, Mark W. Kuemerle | 2020-08-18 |
| 10687420 | Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance | Jean Audet, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada | 2020-06-16 |
| 10598860 | Photonic die fan out package with edge fiber coupling interface and related methods | Koushik Ramachandran, Benjamin V. Fasano | 2020-03-24 |
| 9818682 | Laminate substrates having radial cut metallic planes | Shidong Li | 2017-11-14 |
| 9743526 | Wiring board with stacked embedded capacitors and method of making | Keiichi Hirabayashi, Yoichi Miyazawa, Brian W. Quinlan, Junji Sato | 2017-08-22 |
| 9659131 | Copper feature design for warpage control of substrates | Anson J. Call, Vijayeshwar D. Khanna, Douglas O. Powell, David J. Russell | 2017-05-23 |
| 9543253 | Method for shaping a laminate substrate | Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng | 2017-01-10 |
| 9305894 | Constrained die adhesion cure process | Vijayeshwar D. Khanna, Oswald J. Mantilla | 2016-04-05 |
| 9293439 | Electronic module assembly with patterned adhesive array | Elaine Cyr, Benjamin V. Fasano, Paul F. Fortier, Marcus E. Interrante, Roger Lam +4 more | 2016-03-22 |
| 9129942 | Method for shaping a laminate substrate | — | 2015-09-08 |
| 9105535 | Copper feature design for warpage control of substrates | Anson J. Call, Vijayeshwar D. Khanna, Douglas O. Powell, David J. Russell | 2015-08-11 |
| 9093563 | Electronic module assembly with patterned adhesive array | Elaine Cyr, Benjamin V. Fasano, Paul F. Fortier, Marcus E. Interrante, Roger Lam +4 more | 2015-07-28 |
| 9059240 | Fixture for shaping a laminate substrate | Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng | 2015-06-16 |
| 9048245 | Method for shaping a laminate substrate | Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng | 2015-06-02 |
| 9040388 | Chip assembly with a coreless substrate employing a patterned adhesive layer | — | 2015-05-26 |
| 8378498 | Chip assembly with a coreless substrate employing a patterned adhesive layer | — | 2013-02-19 |
| 7174233 | Quality/reliability system and method in multilevel manufacturing environment | Michael W. Bolch, Biao Cai, George M. Hurtis, Eric Lambert, Shu-Chen Lim +2 more | 2007-02-06 |
| 7095104 | Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same | — | 2006-08-22 |
| 6919515 | Stress accommodation in electronic device interconnect technology for millimeter contact locations | Thomas M. Cipolla, Paul W. Coteus | 2005-07-19 |
| 6774475 | Vertically stacked memory chips in FBGA packages | William F. Beausoleil, N. James Tomassetti | 2004-08-10 |
| 6507122 | Pre-bond encapsulation of area array terminated chip and wafer scale packages | — | 2003-01-14 |
| 6469375 | High bandwidth 3D memory packaging technique | William F. Beausoleil, Michael J. Ellsworth, Jr., William F. Shutler, Norton J. Tomassetti | 2002-10-22 |