JZ

Jiantao Zheng

IBM: 11 patents #9,995 of 70,183Top 15%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
QU Qualcomm: 1 patents #7,512 of 12,104Top 65%
📍 Beacon, NY: #42 of 281 inventorsTop 15%
🗺 New York: #11,369 of 115,490 inventorsTop 10%
Overall (All Time): #381,159 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
9543253 Method for shaping a laminate substrate Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss 2017-01-10
9536805 Power management integrated circuit (PMIC) integration into a processor package Siamak Fazelpour, Mario Francisco Velez, Sun Hyuck Yun, Rajneesh Kumar, Houssam Jomaa 2017-01-03
9366591 Determining magnitude of compressive loading Paul F. Bodenweber, Virendra R. Jadhav, Steven P. Ostrander, Kamal K. Sikka, Jeffrey A. Zitz 2016-06-14
9059240 Fixture for shaping a laminate substrate Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss 2015-06-16
9048245 Method for shaping a laminate substrate Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss 2015-06-02
8794079 Determining magnitude of compressive loading Paul F. Bodenweber, Virendra R. Jadhav, Steven P. Ostrander, Kamal K. Sikka, Jeffrey A. Zitz 2014-08-05
8717043 Determining thermal interface material (TIM) thickness change Paul F. Bodenweber, Virendra R. Jadhav, Kamal K. Sikka, Jeffrey A. Zitz 2014-05-06
8299608 Enhanced thermal management of 3-D stacked die packaging Gerald K. Bartley, David R. Motschman, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei 2012-10-30
8232636 Reliability enhancement of metal thermal interface James N. Humenik, Sushumna Iruvanti, Richard Langlois, Hsichang Liu, Govindarajan Natarajan +4 more 2012-07-31
7875972 Semiconductor device assembly having a stress-relieving buffer layer Virendra R. Jadhav, Kamal K. Sikka 2011-01-25
7834442 Electronic package method and structure with cure-melt hierarchy Bruce K. Furman, Kenneth C. Marston, Jeffrey A. Zitz 2010-11-16
7812438 Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging Virendra R. Jadhav, David L. Questad, Kamal K. Sikka, Xiaojin Wei 2010-10-12
7733655 Lid edge capping load Martin Beaumier, Mohamed Belazzouz, Peter J. Brofman, David L. Edwards, Kamal K. Sikka +1 more 2010-06-08