Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10008316 | Inductor embedded in a package substrate | Charles David Paynter, Ryan David Lane | 2018-06-26 |
| 9536805 | Power management integrated circuit (PMIC) integration into a processor package | Jiantao Zheng, Mario Francisco Velez, Sun Hyuck Yun, Rajneesh Kumar, Houssam Jomaa | 2017-01-03 |
| 9514966 | Apparatus and methods for shielding differential signal pin pairs | Charles David Paynter, Ryan David Lane | 2016-12-06 |
| 9214426 | Highly coupled spiral planar inductors structure at bump to compensate on die excess capacitance of differential I/O | Priyatharshan Pathmanathan, John Loffink | 2015-12-15 |
| 8269348 | IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch | — | 2012-09-18 |
| 6812576 | Fanned out interconnect via structure for electronic package substrates | Mark Patterson | 2004-11-02 |
| 6781229 | Method for integrating passives on-die utilizing under bump metal and related structure | — | 2004-08-24 |
| 6762494 | Electronic package substrate with an upper dielectric layer covering high speed signal traces | Jean-Marc Papillon, Steven J. Martin | 2004-07-13 |
| 6713853 | Electronic package with offset reference plane cutout | Michel Fleury, Mark Patterson | 2004-03-30 |
| 6674646 | Voltage regulation for semiconductor dies and related structure | Khosrow Golshan, Hassan S. Hashemi | 2004-01-06 |
| 6674174 | Controlled impedance transmission lines in a redistribution layer | Surasit Chungpaiboonpatana, Hassan S. Hashemi | 2004-01-06 |
| 6617943 | Package substrate interconnect layout for providing bandpass/lowpass filtering | — | 2003-09-09 |
| 6611048 | Exposed paddle leadframe for semiconductor die packaging | Roberto U. Villanueva | 2003-08-26 |
| 6608363 | Transformer comprising stacked inductors | — | 2003-08-19 |
| 6576983 | Controlled impedance leads in a leadframe for high frequency applications | Hassan S. Hashemi | 2003-06-10 |
| 6566761 | Electronic device package with high speed signal interconnect between die pad and external substrate pad | Laxminarayan Sharma | 2003-05-20 |
| 6534854 | Pin grid array package with controlled impedance pins | Hassan S. Hashemi, Roberto Coccioli | 2003-03-18 |
| 6512285 | High inductance inductor in a semiconductor package | Hassan S. Hashemi, Roberto Coccioli | 2003-01-28 |
| 6501158 | Structure and method for securing a molding compound to a leadframe paddle | Roberto U. Villanueva | 2002-12-31 |
| 6424541 | Electronic device attachment methods and apparatus for forming an assembly | — | 2002-07-23 |
| 6274925 | Low inductance top metal layer design | — | 2001-08-14 |