Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11107766 | Substrate with embedded stacked through-silicon via die | Javier Soto Gonzalez | 2021-08-31 |
| 10804195 | High density embedded interconnects in substrate | Kuiwon Kang, Marcus HSU, Brigham NAVAJA | 2020-10-13 |
| 10651160 | Low profile integrated package | Kuiwon Kang, Christopher Bahr, Layal Rouhana | 2020-05-12 |
| 10622292 | High density interconnects in an embedded trace substrate (ETS) comprising a core layer | Kuiwon Kang | 2020-04-14 |
| 10461032 | Substrate with embedded stacked through-silicon via die | Javier Soto Gonzalez | 2019-10-29 |
| 10157824 | Integrated circuit (IC) package and package substrate comprising stacked vias | Kuiwon Kang, Layal Rouhana, Seongryul Choi | 2018-12-18 |
| 9941158 | Integrated circuit and process for fabricating thereof | Charan Gurumurthy, Islam A. Salama, Ravi Tanikella | 2018-04-10 |
| 9929097 | Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers | Ravi Kiran Nalla, Omar J. Bchir | 2018-03-27 |
| 9679841 | Substrate and method of forming the same | Omar J. Bchir, Kuiwon Kang, Chin-Kwan Kim | 2017-06-13 |
| 9609751 | Package substrate comprising surface interconnect and cavity comprising electroless fill | Omar J. Bchir, Chin-Kwan Kim | 2017-03-28 |
| 9559088 | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same | Javier Soto Gonzalez | 2017-01-31 |
| 9536805 | Power management integrated circuit (PMIC) integration into a processor package | Siamak Fazelpour, Jiantao Zheng, Mario Francisco Velez, Sun Hyuck Yun, Rajneesh Kumar | 2017-01-03 |
| 9460980 | Systems, apparatus, and methods for heat dissipation | Sun Woong Yun, Rajneesh Kumar, Joan Rey Villarba BUOT | 2016-10-04 |
| 9398699 | Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same | Omar J. Bchir | 2016-07-19 |
| 9355898 | Package on package (PoP) integrated device comprising a plurality of solder resist layers | Rajneesh Kumar, David Fraser Rae, Layal Rouhana, Omar J. Bchir | 2016-05-31 |
| 9269681 | Surface finish on trace for a thermal compression flip chip (TCFC) | Omar J. Bchir, Milind Shah, Manuel Aldrete, Chin-Kwan Kim | 2016-02-23 |
| 9040842 | Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers | Ravi Kiran Nalla, Omar J. Bchir | 2015-05-26 |
| 8802556 | Barrier layer on bump and non-wettable coating on trace | Omar J. Bchir, Milind Shah, Manuel Aldrete, Chin-Kwan Kim | 2014-08-12 |
| 8736065 | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same | Javier Soto Gonzalez | 2014-05-27 |
| 8555494 | Method of manufacturing coreless substrate | — | 2013-10-15 |
| 8421245 | Substrate with embedded stacked through-silicon via die | Javier Soto Gonzalez | 2013-04-16 |
| 8276269 | Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same | Omar J. Bchir | 2012-10-02 |
| 8268724 | Alternative to desmear for build-up roughening and copper adhesion promotion | Christine H. Tsau | 2012-09-18 |
| 8067266 | Methods for the fabrication of microelectronic device substrates by attaching two cores together during fabrication | — | 2011-11-29 |
| 8017022 | Selective electroless plating for electronic substrates | Omar J. Bchir, Islam A. Salama | 2011-09-13 |