Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Substrate with embedded stacked through-silicon via die

Substrate with embedded stacked through-silicon via die

US Patent 8421245 · Granted Apr 16, 2013

Estimated economic value: $28,862,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Substrate with embedded stacked through-silicon via die2021
Substrate with embedded stacked through-silicon via die2021
High density embedded interconnects in substrate2020
Low profile integrated package2020
High density interconnects in an embedded trace substrate (ETS) comprising a cor2020
Substrate with embedded stacked through-silicon via die2019
Substrate with embedded stacked through-silicon via die2019
Integrated circuit (IC) package and package substrate comprising stacked vias2018
Integrated circuit and process for fabricating thereof2018
Mechanical adhesion of copper metallization to dielectric with partially cured e2018
Multichip integration with through silicon via (TSV) die embedded in package2017
Substrate and method of forming the same2017