Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12199003 | Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure | Richard S. Graf, Huahung Kao, Ronen Sinai | 2025-01-14 |
| 11594462 | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods | Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li +3 more | 2023-02-28 |
| 11037906 | 3D IC package with RDL interposer and related method | — | 2021-06-15 |
| 11038011 | Metal-insulator-metal capacitors including nanofibers | Lili Cheng, Robert J. Fox | 2021-06-15 |
| 10818570 | Stacked semiconductor devices having dissimilar-sized dies | Daniel G. Berger | 2020-10-27 |
| 10770440 | Micro-LED display assembly | Bartlomiej Jan Pawlak | 2020-09-08 |
| 10741460 | Methods for forming interconnect assemblies with probed bond pads | Owen R. Fay, Kyle K. Kirby, Jaspreet S. Gandhi | 2020-08-11 |
| 10741468 | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods | Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li +3 more | 2020-08-11 |
| 10636776 | Methods of manufacturing RF filters | Md. Sayed Kaysar Bin Rahim, Sukeshwar Kannan | 2020-04-28 |
| 10388631 | 3D IC package with RDL interposer and related method | — | 2019-08-20 |
| 10381304 | Interconnect structure | Mark W. Kuemerle | 2019-08-13 |
| 10283487 | Methods of forming integrated circuit package with thermally conductive pillar | Kathryn C. Rivera | 2019-05-07 |
| 10236263 | Methods and structures for mitigating ESD during wafer bonding | Tanya A. Atanasova, Daniel M. Smith, Daniel W. Fisher, Sukeshwar Kannan | 2019-03-19 |
| 10224286 | Interconnect structure with adhesive dielectric layer and methods of forming same | Kenneth J. Giewont | 2019-03-05 |
| 10193011 | Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach | Srinivasa Banna, Deepak Nayak, Rahul Agarwal | 2019-01-29 |
| 10170389 | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods | Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li +3 more | 2019-01-01 |
| 10163864 | Vertically stacked wafers and methods of forming same | — | 2018-12-25 |
| 10153224 | Backside spacer structures for improved thermal performance | Rahul Agarwal, Haojun Zhang | 2018-12-11 |
| 10134647 | Methods for forming interconnect assemblies with probed bond pads | Owen R. Fay, Kyle K. Kirby, Jaspreet S. Gandhi | 2018-11-20 |
| 10090227 | Back biasing in SOI FET technology | Bartlomiej Jan Pawlak | 2018-10-02 |
| 10083958 | Deep trench metal-insulator-metal capacitors | Sukeshwar Kannan, Somnath Ghosh, Daniel M. Smith | 2018-09-25 |
| 10066303 | Thin NiB or CoB capping layer for non-noble metallic bonding landing pads | Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, George Vakanas | 2018-09-04 |
| 10069490 | Method, apparatus and system for voltage compensation in a semiconductor wafer | Sukeshwar Kannan, Mehdi Sadi | 2018-09-04 |
| 10026883 | Wafer bond interconnect structures | Rahul Agarwal | 2018-07-17 |
| 9865570 | Integrated circuit package with thermally conductive pillar | Kathryn C. Rivera | 2018-01-09 |