Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10794952 | Product performance test binning | Jeanne P. Bickford, Susan K. Lichtensteiger, Nazmul Habib | 2020-10-06 |
| 10067184 | Product performance test binning | Jeanne P. Bickford, Nazmul Habib, Susan K. Lichtensteiger | 2018-09-04 |
| 9429619 | Reliability test screen optimization | Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, Jr. | 2016-08-30 |
| 9310426 | On-going reliability monitoring of integrated circuit chips in the field | Douglas S. Dewey, Pascal A. Nsame, Anthony D. Polson | 2016-04-12 |
| 8421495 | Speed binning for dynamic and adaptive power control | Jeanne P. Bickford, Nazmul Habib, Susan K. Lichtensteiger | 2013-04-16 |
| 8239811 | System and method for wireless and dynamic intra-process measurement of integrated circuit parameters | Phillip L. Corson, Mete Erturk, Ezra D. B. Hall, Anthony J. Perri, Sebastian T. Ventrone | 2012-08-07 |
| 8214651 | Radio frequency identification (RFID) based authentication system and methodology | Shawn P. Fetterolf, Adam J. McPadden | 2012-07-03 |
| 8176323 | Radio frequency identification (RFID) based authentication methodology using standard and private frequency RFID tags | Shawn P. Fetterolf, Adam J. McPadden | 2012-05-08 |
| 8097474 | Integrated circuit chip design flow methodology including insertion of on-chip or scribe line wireless process monitoring and feedback circuitry | Ezra D. B. Hall, Sebastian T. Ventrone | 2012-01-17 |
| 7877714 | System and method to optimize semiconductor power by integration of physical design timing and product performance measurements | Jeanne P. Spence Bickford, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson | 2011-01-25 |
| 7810054 | Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point | Jeanne P. Bickford, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson | 2010-10-05 |
| 7521973 | Clock-skew tuning apparatus and method | Michael R. Quellette, Anthony D. Polson | 2009-04-21 |
| 7487487 | Design structure for monitoring cross chip delay variation on a semiconductor device | Anthony D. Polson, David E. Lackey, Laura S. Chadwick | 2009-02-03 |