Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8880382 | Analyzing a patterning process using a model of yield | Saeed Bagheri, Fook-Luen Heng, Rajiv V. Joshi, Kafai Lai, David O. Melville +3 more | 2014-11-04 |
| 8682634 | Analyzing a patterning process using a model of yield | Saeed Bagheri, Fook-Luen Heng, Rajiv V. Joshi, Kafai Lai, David O. Melville +3 more | 2014-03-25 |
| 8418087 | Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance | Shayak Banerjee, Dureseti Chidambarrao, James A. Culp, Praveen Elakkumanan | 2013-04-09 |
| 8176444 | Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance | Shayak Banerjee, Dureseti Chidambarrao, James A. Culp, Praveen Elakkumanan | 2012-05-08 |
| 8086917 | Methods for characterizing device variation in electronic memory circuits | Ching-Te Chuang, Jae-Joon Kim | 2011-12-27 |
| 7673195 | Circuits and methods for characterizing device variation in electronic memory circuits | Ching-Te Chuang, Jae-Joon Kim | 2010-03-02 |
| 7642864 | Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect | Ching-Te Chuang, Jae-Joon Kim, Tae H. Kim, Pong-Fei Lu, Rahul M. Rao +1 more | 2010-01-05 |
| 7508697 | Self-repairing technique in nano-scale SRAM to reduce parametric failures | Hamid Mahmoodi, Keejong Kim, Kaushik Roy | 2009-03-24 |
| 7319343 | Low power scan design and delay fault testing technique using first level supply gating | Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowhury, Kaushik Roy | 2008-01-15 |
| 7304903 | Sense amplifier circuit | Hamid Mahmoodi, Kaushik Roy | 2007-12-04 |