ND

Nagashyamala R. Dhanwada

IBM: 11 patents #9,995 of 70,183Top 15%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
📍 Fishkill, NY: #73 of 387 inventorsTop 20%
🗺 New York: #12,360 of 115,490 inventorsTop 15%
Overall (All Time): #409,506 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
11301600 Methods for generating a contributor-based power abstract for a device William W. Dungan, David J. Hathaway, Arun Joseph, Gaurav Mittal, Ricardo H. Nigaglioni 2022-04-12
11074391 Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips Leon Sigal, David Kadzov, James D. Warnock 2021-07-27
10572614 Method for efficient localized self-heating analysis using location based DeltaT analysis Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla 2020-02-25
10460048 Methods for generating a contributor-based power abstract for a device William W. Dungan, David J. Hathaway, Arun Joseph, Gaurav Mittal, Ricardo H. Nigaglioni 2019-10-29
10204198 Method for efficient localized self-heating analysis using location based deltat analysis Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla 2019-02-12
9990454 Early analysis and mitigation of self-heating in design flows William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets, Michael R. Scheuermann +3 more 2018-06-05
9424381 Contributor-based power modeling of microprocessor components David J. Hathaway, Victor Zyuban 2016-08-23
9217771 Method for breaking down hardware power into sub-components Anand Haridass, Arun Joseph, Charles R. Lefurgy, Diwesh Pandey 2015-12-22
8898049 System level power profiling of embedded applications executing on virtual multicore system-on-chip platforms Joseph Arun, William W. Dungan 2014-11-25
8234624 System and method for developing embedded software in-situ Robert J. Devins 2012-07-31
7296251 Method of physical planning voltage islands for ASICs and system-on-chip designs Youngsoo Shin, Jingcao Hu 2007-11-13
6799309 Method for optimizing a VLSI floor planner using a path based hyper-edge representation Glenn E. Holmes, Joseph Morrell, Jose L. Neves, Natesan Venkateswaran 2004-09-28