Issued Patents All Time
Showing 26–50 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9618580 | Debugging scan latch circuits using flip devices | — | 2017-04-11 |
| 9614507 | Programmable delay circuit including hybrid fin field effect transistors (finFETs) | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2017-04-04 |
| 9575529 | Voltage droop reduction in a processor | Brian W. Curran, Preetham M. Lobo, Richard F. Rizzolo, Tobias Webel | 2017-02-21 |
| 9552455 | Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications | Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, Leon Sigal | 2017-01-24 |
| 9543463 | Signal distribution in integrated circuit using optical through silicon via | Effendi Leobandung, Dieter Wendel | 2017-01-10 |
| 9543935 | Programmable delay circuit including hybrid fin field effect transistors (finFETs) | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2017-01-10 |
| 9494968 | Clock skew analysis and optimization | Phillip J. Restle | 2016-11-15 |
| 9496447 | Signal distribution in integrated circuit using optical through silicon via | Effendi Leobandung, Dieter Wendel | 2016-11-15 |
| 9088279 | Margin improvement for configurable local clock buffer | Bruce M. Fleischer | 2015-07-21 |
| 8914765 | Power grid generation through modification of an initial power grid based on power grid analysis | Leon Sigal | 2014-12-16 |
| 8875084 | Optimal spare latch selection for metal-only ECOs | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2014-10-28 |
| 8589842 | Device-based random variability modeling in timing analysis | Manjul Bhushan, Eric Jason Fluhr, Stephen G. Shuma, Debjit Sinha, Chandramouli Visweswariah +1 more | 2013-11-19 |
| 8354858 | Apparatus and method for hardening latches in SOI CMOS devices | Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges +2 more | 2013-01-15 |
| 8117579 | LSSD compatibility for GSD unified global clock buffers | Wendel Dieter, David E. Lackey, William V. Huott, Leon Sigal, Louis Bernard Bushard +1 more | 2012-02-14 |
| 8104014 | Regular local clock buffer placement and latch clustering by iterative optimization | Ruchir Puri, Haifeng Qian, Chin Ngai Sze | 2012-01-24 |
| 7962811 | Scan chain disable function for power saving | Sang Hoo Dhong, Joel A. Silberman, Osamu Takahashi, Dieter Wendel | 2011-06-14 |
| 7888959 | Apparatus and method for hardening latches in SOI CMOS devices | Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges +2 more | 2011-02-15 |
| 7719315 | Programmable local clock buffer | Hung C. Ngo, Jente B. Kuang, Dieter Wendel | 2010-05-18 |
| 7693701 | Structure for a configurable low power high fan-in multiplexer | Owen Chiang, Christopher McCall Durham, Peter Juergen Klim | 2010-04-06 |
| 7643981 | Pulse waveform timing in EinsTLT templates | Sang-Yeol Lee, Vasant Rao, Jeffrey P. Soreff, David W. Winston | 2010-01-05 |
| 7633316 | Transmission gate multiplexer | Owen Chiang, Christopher McCall Durham, Peter Juergen Klim, Robert N. Krentler | 2009-12-15 |
| 7589565 | Low-power multi-output local clock buffer | Leon Sigal, Dieter Wendel | 2009-09-15 |
| 7466164 | Method and apparatus for a configurable low power high fan-in multiplexer | Owen Chiang, Christopher McCall Durham, Peter Juergen Klim | 2008-12-16 |
| 7466165 | Transmission gate multiplexer | Owen Chiang, Christopher McCall Durham, Peter Juergen Klim, Robert N. Krentler | 2008-12-16 |
| 7459950 | Pulsed local clock buffer (LCB) characterization ring oscillator | Hung C. Ngo, Jente B. Kuang, Dieter Wendel | 2008-12-02 |