Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12346673 | Large language models utilizing element-wise operation-fusion | Sujan Kumar Gonugondla, Bohan Yao, Xiaokai Wei, Jiacheng Guo, Vamshidhar Krishnamurthy Dantu +8 more | 2025-07-01 |
| 11922285 | Dividing training data for aggregating results of multiple machine learning elements | — | 2024-03-05 |
| 11687783 | L2-nonexpansive neural networks | Mark N. Wegman | 2023-06-27 |
| 11630987 | Neural belief reasoner | — | 2023-04-18 |
| 11625554 | L2-nonexpansive neural networks | Mark N. Wegman | 2023-04-11 |
| 11556794 | Facilitating neural networks | Mark N. Wegman | 2023-01-17 |
| 11521014 | L2-nonexpansive neural networks | Mark N. Wegman | 2022-12-06 |
| 10963794 | Concept analysis operations utilizing accelerators | Emrah Acar, Rajesh Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri +1 more | 2021-03-30 |
| 10948955 | Chip transient temperature predictor | Chen-Yong Cher | 2021-03-16 |
| 10620659 | Clock network analysis using harmonic balance | Peter Feldmann | 2020-04-14 |
| 10528097 | Chip transient temperature predictor | Chen-Yong Cher | 2020-01-07 |
| 10373057 | Concept analysis operations utilizing accelerators | Emrah Acar, Rajesh Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri +1 more | 2019-08-06 |
| 10310812 | Matrix ordering for cache efficiency in performing large sparse matrix operations | Emrah Acar, Rajesh Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri +1 more | 2019-06-04 |
| 9946800 | Ranking related objects using blink model based relation strength determinations | Hui Wan | 2018-04-17 |
| 9798847 | Cross-hierarchy interconnect adjustment for power recovery | Christopher J. Berry, Ricardo H. Nigaglioni, Sourav Saha | 2017-10-24 |
| 9734270 | Control path power adjustment for chip design | Christopher J. Berry, Kaustav Guha, Jose L. Neves, Sourav Saha | 2017-08-15 |
| 9703910 | Control path power adjustment for chip design | Christopher J. Berry, Kaustav Guha, Jose L. Neves, Sourav Saha | 2017-07-11 |
| 9684757 | Cross-hierarchy interconnect adjustment for power recovery | Christopher J. Berry, Ricardo H. Nigaglioni, Sourav Saha | 2017-06-20 |
| 9606934 | Matrix ordering for cache efficiency in performing large sparse matrix operations | Emrah Acar, Rajesh Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri +1 more | 2017-03-28 |
| 9552451 | Cross-hierarchy interconnect adjustment for power recovery | Christopher J. Berry, Ricardo H. Nigaglioni, Sourav Saha | 2017-01-24 |
| 9251340 | Malicious activity detection of a processing thread | Chen-Yong Cher, Eren Kursun | 2016-02-02 |
| 9218488 | Malicious activity detection of a processing thread | Chen-Yong Cher, Eren Kursun | 2015-12-22 |
| 9172714 | Malicious activity detection of a functional unit | Chen-Yong Cher, Eren Kursun | 2015-10-27 |
| 9088597 | Malicious activity detection of a functional unit | Chen-Yong Cher, Eren Kursun | 2015-07-21 |
| 8775996 | Direct current circuit analysis based clock network design | Charles J. Alpert, Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Phillip J. Restle +2 more | 2014-07-08 |