Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8117579 | LSSD compatibility for GSD unified global clock buffers | James D. Warnock, Wendel Dieter, David E. Lackey, William V. Huott, Leon Sigal +1 more | 2012-02-14 |
| 7844869 | Implementing enhanced LBIST testing of paths including arrays | Todd A. Christensen, Jesse D. Smith | 2010-11-30 |
| 7797600 | Method and apparatus for testing a ring of non-scan latches with logic built-in self-test | Nathan P. Chelstrom, Naoki Kiryu, David J. Krolak | 2010-09-14 |
| 7733722 | Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse | Anthony Gus Aipperspach, David H. Allen, Phil C. Paone, Gregory J. Uhlmann | 2010-06-08 |
| 7689950 | Implementing Efuse sense amplifier testing without blowing the Efuse | Anthony Gus Aipperspach, David H. Allen, Phil C. Paone, Gregory J. Uhlmann | 2010-03-30 |
| 7562267 | Methods and apparatus for testing a memory | Anthony Gus Aipperspach, Akihiko Fukui, Garrett Stephen Koch | 2009-07-14 |
| 7489572 | Method for implementing eFuse sense amplifier testing without blowing the eFuse | Anthony Gus Aipperspach, David H. Allen, Phil C. Paone, Gregory J. Uhlmann | 2009-02-10 |
| 7406640 | Method and apparatus for testing a ring of non-scan latches with logic built-in self-test | Nathan P. Chelstrom, Naoki Kiryu, David J. Krolak | 2008-07-29 |
| 7318182 | Memory array manufacturing defect detection system and method | Sang Hoo Dhong, Brian Flachs, Osamu Takahashi, Michael Brian White | 2008-01-08 |
| 7080298 | Circuit apparatus and method for testing integrated circuits using weighted pseudo-random test patterns | Naoki Kiryu | 2006-07-18 |
| 7055077 | Systems and methods for circuit testing | Naoki Kiryu | 2006-05-30 |
| 6909274 | Signal pin tester for AC defects in integrated circuits | Frank W. Angelotti, Matthew S. Grady, Scott A. Strissel | 2005-06-21 |
| 6590382 | Signal pin tester for AC defects in integrated circuits | Frank W. Angelotti, Matthew S. Grady, Scott A. Strissel | 2003-07-08 |
| 5819072 | Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints | Peter B. Criswell, Douglas A. Fuller, James E. Rezek, Richard F. Paul | 1998-10-06 |
| 4873630 | Scientific processor to support a host processor referencing common memory | John T. Rusterholz, Archie E. Lahti, Larry L. Byers, James R. Hamstra, Charles J. Homan | 1989-10-10 |
| 4736292 | Electronic data processing system overlaid jump mechanism | Michael Danilenko, Larry L. Byers | 1988-04-05 |
| 4594680 | Apparatus for performing quadratic convergence division in a large data processing system | John R. Schomburg | 1986-06-10 |