JR

John T. Rusterholz

UN Unisys: 8 patents #139 of 2,015Top 7%
CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
SP Sperry: 1 patents #355 of 841Top 45%
📍 Roseville, MN: #85 of 611 inventorsTop 15%
🗺 Minnesota: #6,858 of 52,454 inventorsTop 15%
Overall (All Time): #473,239 of 4,157,543Top 15%
11
Patents All Time

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDate
5912820 Method and apparatus for distributing a clock tree within a hierarchical circuit design Joseph P. Kerzman, James E. Rezek 1999-06-15
5864838 System and method for reordering lookup table entries when table address bits are reordered 1999-01-26
5781903 System and method for reordering lookup table entries when table address bits are inverted 1998-07-14
5696693 Method for placing logic functions and cells in a logic design using floor planning by analogy Mark D. Aubel, Arthur F. Boehm, Joseph P. Kerzman, James E. Rezek, Richard F. Paul 1997-12-09
5634113 Method for generating a preferred processing order and for detecting cycles in a directed graph used to represent system component connectivity 1997-05-27
4945479 Tightly coupled scientific processing system Charles J. Homan, Lowell E. Brown, Donald B. Bennett, Robert J. Malnati, James R. Hamstra 1990-07-31
4873630 Scientific processor to support a host processor referencing common memory Archie E. Lahti, Louis Bernard Bushard, Larry L. Byers, James R. Hamstra, Charles J. Homan 1989-10-10
4858115 Loop control mechanism for scientific processor James R. Hamstra 1989-08-15
4839845 Method and apparatus for performing a vector reduction John R. Schomburg 1989-06-13
4706191 Local store for scientific vector processor James R. Hamstra, Howard A. Koehler, David J. Tanglin 1987-11-10
4691279 Instruction buffer for a digital data processing system Michael Danilenko, Archie E. Lahti 1987-09-01