Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9098669 | Boundary latch and logic placement to satisfy timing constraints | Charles J. Alpert, Gregory F. Ford, Zhuo Li, Chin Ngai Sze, Paul G. Villarrubia +1 more | 2015-08-04 |
| 8839177 | Method and system allowing for semiconductor design rule optimization | Jeanne P. Bickford, Howard S. Landis, Michael Ross, Mark S. Styduhar, Charles H. Windisch, Jr. | 2014-09-16 |
| 6910200 | Method and apparatus for associating selected circuit instances and for performing a group operation thereon | Joseph P. Kerzman, James M. Nead, James E. Rezek | 2005-06-21 |
| 6754879 | Method and apparatus for providing modularity to a behavioral description of a circuit design | Merwin H. Alferness, Frederick H. Hathaway | 2004-06-22 |
| 6701289 | Method and apparatus for using a placement tool to manipulate cell substitution lists | Robert E. Garnett, Joseph P. Kerzman, James E. Rezek | 2004-03-02 |
| 6684376 | Method and apparatus for selecting components within a circuit design database | Joseph P. Kerzman, James E. Rezek, Merwin H. Alferness | 2004-01-27 |
| 6516456 | Method and apparatus for selectively viewing nets within a database editor tool | Robert E. Garnett, Joseph P. Kerzman, James E. Rezek | 2003-02-04 |
| 6029205 | System architecture for improved message passing and process synchronization between concurrently executing processes | Merwin H. Alferness, Charles R. Caldarale, James W. Douglas, David C. Johnson, David R. Johnson +7 more | 2000-02-22 |
| 5696693 | Method for placing logic functions and cells in a logic design using floor planning by analogy | Arthur F. Boehm, Joseph P. Kerzman, James E. Rezek, John T. Rusterholz, Richard F. Paul | 1997-12-09 |