Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8769164 | Methods and apparatus for allocating bandwidth for a network processor | William John Goetzinger, Kent Harold Haselhorst, Lonny Lambrecht, Joshua W. Rensch | 2014-07-01 |
| 7130270 | Method and apparatus for varying bandwidth provided to virtual channels in a virtual path | Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard | 2006-10-31 |
| 7069557 | Network processor which defines virtual paths without using logical path descriptors | — | 2006-06-27 |
| 6754879 | Method and apparatus for providing modularity to a behavioral description of a circuit design | Mark D. Aubel, Frederick H. Hathaway | 2004-06-22 |
| 6684376 | Method and apparatus for selecting components within a circuit design database | Joseph P. Kerzman, James E. Rezek, Mark D. Aubel | 2004-01-27 |
| 6629236 | Master-slave latch circuit for multithreaded processing | Anthony Gus Aipperspach, Gregory J. Uhlmann | 2003-09-30 |
| 6278959 | Method and system for monitoring the performance of a data processing system | — | 2001-08-21 |
| 6247064 | Enqueue instruction in a system architecture for improved message passing and process synchronization | Charles R. Caldarale, David C. Johnson, David R. Johnson, James R. McBreen, Wayne D. Ward | 2001-06-12 |
| 6029205 | System architecture for improved message passing and process synchronization between concurrently executing processes | Mark D. Aubel, Charles R. Caldarale, James W. Douglas, David C. Johnson, David R. Johnson +7 more | 2000-02-22 |
| 5966515 | Parallel emulation system and method | — | 1999-10-12 |
| 5896522 | Selective emulation interpretation using transformed instructions | Wayne D. Ward | 1999-04-20 |
| 5701316 | Method for generating an internet protocol suite checksum in a single macro instruction | Peter B. Criswell, David R. Johnson, James R. McBreen | 1997-12-23 |
| 5611065 | Address prediction for relative-to-absolute addressing | Joseph P. Kerzman, John Z. Nguyen | 1997-03-11 |
| 5602998 | Dequeue instruction in a system architecture for improved message passing and process synchronization | Charles R. Caldarale, David C. Johnson, David R. Johnson, James R. McBreen, Wayne D. Ward | 1997-02-11 |
| 5577259 | Instruction processor control system using separate hardware and microcode control signals to control the pipelined execution of multiple classes of machine instructions | John S. Kuslak, Mark A. Vasquez, Joseph P. Kerzman, Eric Collins | 1996-11-19 |
| 5555396 | Hierarchical queuing in a system architecture for improved message passing and process synchronization | Charles R. Caldarale, David R. Johnson, Joseph P. Kerzman, James R. McBreen | 1996-09-10 |
| 5414821 | Method of and apparatus for rapidly loading addressing environment by checking and loading multiple registers using a specialized instruction | John Z. Nguyen | 1995-05-09 |
| 5379392 | Method of and apparatus for rapidly loading addressing registers | John Z. Nguyen | 1995-01-03 |
| 5363490 | Apparatus for and method of conditionally aborting an instruction within a pipelined architecture | Eric Collins | 1994-11-08 |