Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7831807 | System and method for expanding the instruction set of an instruction processor | David C. Johnson | 2010-11-09 |
| 7451270 | System and method for detecting and correcting errors in a control system | — | 2008-11-11 |
| 6654875 | Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator | Thomas Hartnett, John S. Kuslak, Wayne D. Ward | 2003-11-25 |
| 5931940 | Testing and string instructions for data stored on memory byte boundaries in a word oriented machine | Richard M. Shelton | 1999-08-03 |
| 5819072 | Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints | Louis Bernard Bushard, Douglas A. Fuller, James E. Rezek, Richard F. Paul | 1998-10-06 |
| 5701316 | Method for generating an internet protocol suite checksum in a single macro instruction | Merwin H. Alferness, David R. Johnson, James R. McBreen | 1997-12-23 |
| 5168501 | Method for checking hardware errors | — | 1992-12-01 |
| 5081629 | Fault isolation for multiphase clock signals supplied to dual modules which are checked by comparison using residue code generators | Michael J. Stella | 1992-01-14 |
| 5077739 | Method for isolating failures of clear signals in instruction processors | — | 1991-12-31 |
| 4989172 | Apparatus and method for checking start signals | — | 1991-01-29 |
| 4943969 | Isolation for failures of input signals supplied to dual modules which are checked by comparison | — | 1990-07-24 |
| 4924467 | System for checking duplicate logic using complementary residue codes to achieve high error coverage with a minimum of interface signals | — | 1990-05-08 |
| 4595911 | Programmable data reformat system | Glen R. Kregness, Clarence W. DeKarske | 1986-06-17 |
| 4556978 | Error checked high speed shift matrix | Glen R. Kregness, Clarence W. DeKarske | 1985-12-03 |
| 4528640 | Method and a means for checking normalizing operations in a computer device | — | 1985-07-09 |
| 4366548 | Adder for exponent arithmetic | Glen R. Kregness | 1982-12-28 |