Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9928210 | Constrained backup image defragmentation optimization within deduplication system | Xianbo Zhang, Benjamin Potvien, Weibao Wu, Satyajit Gorhe Parlikar | 2018-03-27 |
| 9830231 | Processes and methods for client-side fingerprint caching to improve deduplication system backup performance | Xianbo Zhang, Weibao Wu | 2017-11-28 |
| 9298707 | Efficient data storage and retrieval for backup systems | Xianbo Zhang | 2016-03-29 |
| 8874520 | Processes and methods for client-side fingerprint caching to improve deduplication system backup performance | Xianbo Zhang, Weibao Wu | 2014-10-28 |
| 8301772 | Method and apparatus for allocating resources among backup tasks in a data backup system | Michael Zeis, Adonijah Park | 2012-10-30 |
| 7389407 | Central control system and method for using state information to model inflight pipelined instructions | John S. Kuslak | 2008-06-17 |
| 7058793 | Pipeline controller for providing independent execution between the preliminary and advanced stages of a synchronous pipeline | John S. Kuslak, Gary J. Lucas | 2006-06-06 |
| 6839833 | Pipeline depth controller for an instruction processor | John S. Kuslak, Leroy J. Longworth | 2005-01-04 |
| 6754295 | Method and apparatus for synchronizing data transmission and reception over a network | — | 2004-06-22 |
| 6751756 | First level cache parity error inject | John S. Kuslak, Douglas A. Fuller | 2004-06-15 |
| 6654875 | Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator | John S. Kuslak, Peter B. Criswell, Wayne D. Ward | 2003-11-25 |
| 6167479 | System and method for testing interrupt processing logic within an instruction processor | John S. Kuslak, David R. Schroeder | 2000-12-26 |