Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020030 | Command delay | Bruce Dunlop, Edward C. McGlaughlin | 2024-06-25 |
| 11868267 | Access unit and management segment memory operations | Edward C. McGlaughlin, Joseph M. Jeddeloh | 2024-01-09 |
| 11544144 | Read recovery control circuitry | Richard D. Wiita, Edward C. McGlaughlin | 2023-01-03 |
| 11301391 | Access unit and management segment memory operations | Edward C. McGlaughlin, Joseph M. Jeddeloh | 2022-04-12 |
| 11093244 | Command delay | Bruce Dunlop, Edward C. McGlaughlin | 2021-08-17 |
| 11023317 | Read recovery control circuitry | Richard D. Wiita, Edward C. McGlaughlin | 2021-06-01 |
| 10817430 | Access unit and management segment memory operations | Edward C. McGlaughlin, Joseph M. Jeddeloh | 2020-10-27 |
| 7827455 | System and method for detecting glitches on a high-speed interface | Nathan A. Eckel, Peter Levinshteyn | 2010-11-02 |
| 7114063 | Condition indicator for use by a conditional branch instruction | Lawrence R. Fontaine, John S. Kuslak, Michael David Pelarski | 2006-09-26 |
| 7058793 | Pipeline controller for providing independent execution between the preliminary and advanced stages of a synchronous pipeline | Thomas Hartnett, John S. Kuslak | 2006-06-06 |
| 6108761 | Method of and apparatus for saving time performing certain transfer instructions | David C. Johnson, John S. Kuslak | 2000-08-22 |
| 6081881 | Method of and apparatus for speeding up the execution of normal extended mode transfer instructions | David C. Johnson | 2000-06-27 |
| 5875201 | Second level cache having instruction cache parity error control | Mitchell A. Bauman, Donald W. Mackenthun, James L. Federici | 1999-02-23 |
| 5872910 | Parity-error injection system for an instruction processor | John S. Kuslak, Nguyen T. Tran | 1999-02-16 |
| 5867699 | Instruction flow control for an instruction processor | John S. Kuslak, David C. Johnson, Kenneth L. Engelbrecht | 1999-02-02 |
| 5724533 | High performance instruction data path | John S. Kuslak | 1998-03-03 |
| 5644759 | Apparatus and method for processing a jump instruction preceded by a skip instruction | Ronald G. Arnold | 1997-07-01 |
| 5408629 | Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system | Kenichi Tsuchiva, Glen R. Kregness, Ferris T. Price deceased | 1995-04-18 |