Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9021454 | Operand and limits optimization for binary translation system | Judge William Yohn, Feng-Jung Kao, James R. McBreen, James Merton | 2015-04-28 |
| 7634709 | Familial correction with non-familial double bit error detection | Eugene A. Rodi | 2009-12-15 |
| 7343515 | System and method for performing error recovery in a data processing system having multiple processing partitions | R. Lee Gilbertson, Penny L. Svenkeson | 2008-03-11 |
| 7277825 | Apparatus and method for analyzing performance of a data processing system | Marwan A. Orfali, Myoungran Kim | 2007-10-02 |
| 7260677 | Programmable system and method for accessing a shared memory | Kelvin S. Vartti, Ross M. Weber | 2007-08-21 |
| 7213109 | System and method for providing speculative ownership of cached data based on history tracking | Joseph S. Schibinger | 2007-05-01 |
| 7167955 | System and method for testing and initializing directory store memory | Justin Neils, John S. Jensen, Eugene A. Rodi, Bart E. Reigstad | 2007-01-23 |
| 7047322 | System and method for performing conflict resolution and flow control in a multiprocessor system | Matthew D. Rench, James L. DePenning | 2006-05-16 |
| 7032079 | System and method for accelerating read requests within a multiprocessor system | R. Lee Gilbertson, Jerome G. Carlin | 2006-04-18 |
| 6981106 | System and method for accelerating ownership within a directory-based memory system | Douglas H. Bloom | 2005-12-27 |
| 6973548 | Data acceleration mechanism for a multiprocessor shared memory system | Kelvin S. Vartti, Ross M. Weber, Ronald G. Arnold | 2005-12-06 |
| 6868482 | Method and apparatus for parallel store-in second level caching | Donald W. Mackenthun, Donald C. Englin | 2005-03-15 |
| 6799252 | High-performance modular memory system with crossbar connections | — | 2004-09-28 |
| 6728835 | Leaky cache mechanism | Conrad S. Shimada, Kelvin S. Vartti, William L. Borgerding | 2004-04-27 |
| 6594785 | System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions | Roger L. Gilbertson, Penny L. Svenkeson, James L. DePenning, Michael Haupt, Donald R. Kalvestrand +3 more | 2003-07-15 |
| 6587931 | Directory-based cache coherency system supporting multiple instruction processor and input/output caches | Eugene A. Rodi, Douglas E. Morrissey | 2003-07-01 |
| 6480927 | High-performance modular memory system with crossbar connections | — | 2002-11-12 |
| 6477620 | Cache-level return data by-pass system for a hierarchical memory | Roger L. Gilbertson, Donald R. Kalvestrand, Joseph S. Schibinger, Daniel S. Tokoly | 2002-11-05 |
| 6457101 | System and method for providing the speculative return of cached data within a hierarchical memory system | Roger L. Gilbertson, Donald R. Kalvestrand, Joseph S. Schibinger, Daniel S. Tokoly | 2002-09-24 |
| 6453276 | Method and apparatus for efficiently generating test input for a logic simulator | — | 2002-09-17 |
| 6438659 | Directory based cache coherency system supporting multiple instruction processor and input/output caches | Eugene A. Rodi, Douglas E. Morrissey | 2002-08-20 |
| 6434641 | System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme | Michael Haupt | 2002-08-13 |
| 6415364 | High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems | Eugene A. Rodi | 2002-07-02 |
| 6381715 | System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module | Roger L. Gilbertson, Eugene A. Rodi | 2002-04-30 |
| 6356991 | Programmable address translation system | Roger L. Gilbertson | 2002-03-12 |