Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6336088 | Method and apparatus for synchronizing independently executing test lists for design verification | Douglas H. Bloom, Joseba M. Desubijan, Larry L. Byers | 2002-01-01 |
| 6279098 | Method of and apparatus for serial dynamic system partitioning | Lewis A. Boone, Donald Schroeder | 2001-08-21 |
| 6226716 | Test driver for use in validating a circuit design | David L. Ganske | 2001-05-01 |
| 6199135 | Source synchronous transfer scheme for a high speed memory interface | David A. Maahs, Robert M. Malek | 2001-03-06 |
| 6189078 | System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency | Michael Haupt | 2001-02-13 |
| 6182112 | Method of and apparatus for bandwidth control of transfers via a bi-directional interface | Robert M. Malek, Roger L. Gilbertson | 2001-01-30 |
| 6178466 | System for maximizing bandpass on an interface directly coupling two units where the interface has independently operative data and address interconnections, and computer sysem employing same. | Roger L. Gilbertson | 2001-01-23 |
| 6167489 | System and method for bypassing supervisory memory intervention for data transfers between devices having local memories | Roger L. Gilbertson, Michael Haupt | 2000-12-26 |
| 6122711 | Method of and apparatus for store-in second level cache flush | Donald W. Mackenthun, Donald C. Englin | 2000-09-19 |
| 6055607 | Interface queue with bypassing capability for main storage unit | James L. Federici | 2000-04-25 |
| 6052760 | Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks | Arthur J. Nilson, Douglas E. Morrissey | 2000-04-18 |
| 6049845 | System and method for providing speculative arbitration for transferring data | Joseph S. Schibinger, Donald R. Kalvestrand, Douglas E. Morrissey | 2000-04-11 |
| 6014709 | Message flow protocol for avoiding deadlocks | Robert C. Gulick, Douglas E. Morrissey | 2000-01-11 |
| 5960455 | Scalable cross bar type storage controller | — | 1999-09-28 |
| 5946710 | Selectable two-way, four-way double cache interleave scheme | Donald C. Englin | 1999-08-31 |
| 5915128 | Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register | James L. Federici | 1999-06-22 |
| 5875472 | Address conflict detection system employing address indirection for use in a high-speed multi-processor system | Donald C. Englin, Donald W. Mackenthun | 1999-02-23 |
| 5875119 | Computer performance monitoring using time-division multiplexing | Michael Fahland, Donald W. Mackenthun, Nguyen T. Tran | 1999-02-23 |
| 5875201 | Second level cache having instruction cache parity error control | Donald W. Mackenthun, Gary J. Lucas, James L. Federici | 1999-02-23 |
| 5875462 | Multi-processor data processing system with multiple second level caches mapable to all of addressable memory | Donald C. Englin, Mark L. Balding | 1999-02-23 |
| 5860093 | Reduced instruction processor/storage controller interface | Donald C. Englin | 1999-01-12 |
| 5832304 | Memory queue with adjustable priority and conflict detection | Jerome G. Carlin, Roger L. Gilbertson | 1998-11-03 |
| 5822766 | Main memory interface for high speed data transfer | David M. Purdham | 1998-10-13 |
| 5680571 | Multi-processor data processing system with multiple, separate instruction and operand second level caches | — | 1997-10-21 |
| 5678026 | Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues | Kelvin S. Vartti | 1997-10-14 |