Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7797472 | Method and apparatus for providing overlapping defer phase responses | Gregory B. Wiedenman, Nathan A. Eckel | 2010-09-14 |
| 7533223 | System and method for handling memory requests in a multiprocessor shared memory system | Ross M. Weber | 2009-05-12 |
| 7496715 | Programmable cache management system and method | Ross M. Weber | 2009-02-24 |
| 7299311 | Apparatus and method for arbitrating for a resource group with programmable weights | Chad M. Sepeda, Ross M. Weber | 2007-11-20 |
| 7260677 | Programmable system and method for accessing a shared memory | Ross M. Weber, Mitchell A. Bauman | 2007-08-21 |
| 7222222 | System and method for handling memory requests in a multiprocessor shared memory system | Ross M. Weber | 2007-05-22 |
| 7120836 | System and method for increasing cache hit detection performance | Donald C. Englin | 2006-10-10 |
| 7065614 | System and method for maintaining memory coherency within a multi-processor data processing system | James A. Williams, Donald C. Englin | 2006-06-20 |
| 6993630 | Data pre-fetch system and method for a cache memory | James A. Williams, Robert H. Andrighetti, Conrad S. Shimada, Donald C. Englin | 2006-01-31 |
| 6973541 | System and method for initializing memory within a data processing system | James A. Williams, Robert H. Andrighetti, Conrad S. Shimada, Stephen Sutter, Chad M. Sonmore | 2005-12-06 |
| 6973548 | Data acceleration mechanism for a multiprocessor shared memory system | Ross M. Weber, Mitchell A. Bauman, Ronald G. Arnold | 2005-12-06 |
| 6934810 | Delayed leaky write system and method for a cache memory | James A. Williams, Robert H. Andrighetti, David P. G. Williams | 2005-08-23 |
| 6928517 | Method for avoiding delays during snoop requests | Donald C. Englin, Donald W. Mackenthun | 2005-08-09 |
| 6857049 | Method for managing flushes with the cache | Donald C. Englin, James L. Federici | 2005-02-15 |
| 6816952 | Lock management system and method for use in a data processing system | Wayne D. Ward, Hans C. Mikkelsen | 2004-11-09 |
| 6799249 | Split control for IP read and write cache misses | Donald C. Englin | 2004-09-28 |
| 6728835 | Leaky cache mechanism | Mitchell A. Bauman, Conrad S. Shimada, William L. Borgerding | 2004-04-27 |
| 6697925 | Use of a cache ownership mechanism to synchronize multiple dayclocks | James L. Federici, Robert M. Malek, Lewis A. Boone | 2004-02-24 |
| 6625698 | Method and apparatus for controlling memory storage locks based on cache line ownership | — | 2003-09-23 |
| 6374332 | Cache control system for performing multiple outstanding ownership requests | Donald W. Mackenthun | 2002-04-16 |
| 5678026 | Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues | Mitchell A. Bauman | 1997-10-14 |
| 5574753 | Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs | Thomas T. Kubista, Ferris T. Price, deceased | 1996-11-12 |
| 5422918 | Clock phase detecting system for detecting the phase difference between two clock phases regardless of which of the two clock phases leads the other | Thomas T. Kubista | 1995-06-06 |
| 5381416 | Detection of skew fault in a multiple clock system | Gregory B. Wiedenman | 1995-01-10 |