Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7673190 | System and method for detecting and recovering from errors in an instruction stream of an electronic data processing system | Kenneth L. Engelbrecht, Lawrence R. Fontaine, Conrad S. Shimada | 2010-03-02 |
| 7389407 | Central control system and method for using state information to model inflight pipelined instructions | Thomas Hartnett | 2008-06-17 |
| 7114063 | Condition indicator for use by a conditional branch instruction | Lawrence R. Fontaine, Gary J. Lucas, Michael David Pelarski | 2006-09-26 |
| 7093190 | System and method for handling parity errors in a data processing system | Nadeem T. Chaudhry, Ashiqur Rahman | 2006-08-15 |
| 7058793 | Pipeline controller for providing independent execution between the preliminary and advanced stages of a synchronous pipeline | Thomas Hartnett, Gary J. Lucas | 2006-06-06 |
| 6839833 | Pipeline depth controller for an instruction processor | Thomas Hartnett, Leroy J. Longworth | 2005-01-04 |
| 6751756 | First level cache parity error inject | Thomas Hartnett, Douglas A. Fuller | 2004-06-15 |
| 6654875 | Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator | Thomas Hartnett, Peter B. Criswell, Wayne D. Ward | 2003-11-25 |
| 6167479 | System and method for testing interrupt processing logic within an instruction processor | Thomas Hartnett, David R. Schroeder | 2000-12-26 |
| 6108761 | Method of and apparatus for saving time performing certain transfer instructions | David C. Johnson, Gary J. Lucas | 2000-08-22 |
| 5911083 | Programmable processor execution rate controller | — | 1999-06-08 |
| 5905881 | Delayed state writes for an instruction processor | Nguyen T. Tran, Lawrence R. Fontaine, Kenneth L. Engelbrecht | 1999-05-18 |
| 5872910 | Parity-error injection system for an instruction processor | Gary J. Lucas, Nguyen T. Tran | 1999-02-16 |
| 5867699 | Instruction flow control for an instruction processor | David C. Johnson, Gary J. Lucas, Kenneth L. Engelbrecht | 1999-02-02 |
| 5761740 | Method of and apparatus for rapidly loading addressing registers | David C. Johnson, Lawrence R. Fontaine | 1998-06-02 |
| 5724533 | High performance instruction data path | Gary J. Lucas | 1998-03-03 |
| 5675768 | Store software instrumentation package instruction | Nguyen T. Tran | 1997-10-07 |
| 5577259 | Instruction processor control system using separate hardware and microcode control signals to control the pipelined execution of multiple classes of machine instructions | Merwin H. Alferness, Mark A. Vasquez, Joseph P. Kerzman, Eric Collins | 1996-11-19 |
| 5434986 | Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction | Buraimoh Adebayo | 1995-07-18 |